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Atomic crystals resistive switching memory

Chinese Physics B 2017年第3期26卷 1-16页

作者：刘春森张卫周鹏 State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai 200433 China

Facing the growing data storage and computing demands, a high accessing speed memory with low power and non- volatile character is urgently needed. Resistive access random memory with 4F2 cell size, switching in sub-nanosecond, cycling endurances of over 1012 cycles, and information retention exceeding 10 years, is considered as promising next- generation non-volatile memory. However, the energy per bit is still too high to compete against static random access memory and dynamic random access memory. The sneak leakage path and metal film sheet resistance issues hinder the further scaling down. The variation of resistance between different devices and even various cycles in the same device, hold resistive access random memory back from commercialization. The emerging of atomic crystals, possessing fine interface without dangling bonds in low dimension, can provide atomic level solutions for the obsessional issues. Moreover, the unique properties of atomic crystals also enable new type resistive switching memories, which provide a brand-new direction for the resistive access random memory.

关键词： atomic crystals two-dimensional materials resistive switching memory

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Distributed machine learning for wireless communication networks: Techniques, architectures, and applications

arXiv

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arXiv 2020年

作者： Hu, Shuyan Chen, Xiaojing Ni, Wei Hossain, Ekram Wang, Xin State Key Laboratory of ASIC and System School of Information Science and Technology Fudan University Shanghai200433 China Shanghai Institute for Advanced Communication and Data Science Shanghai University Shanghai200444 China SydneyNSW2122 Australia Department of Electrical and Computer Engineering University of Manitoba WinnipegMBR3T 5V6 Canada State Key Laboratory of ASIC and System Shanghai Institute for Advanced Communication and Data Science Department of Communication Science and Engineering Fudan University Shanghai200433 China

Distributed machine learning (DML) techniques, such as federated learning, partitioned learning, and distributed reinforcement learning, have been increasingly applied to wireless communications. This is due to improved capabilities of terminal devices, explosively growing data volume, congestion in the radio interfaces, and increasing concern of data privacy. The unique features of wireless systems, such as large scale, geographically dispersed deployment, user mobility, and massive amount of data, give rise to new challenges in the design of DML techniques. There is a clear gap in the existing literature in that the DML techniques are yet to be systematically reviewed for their applicability to wireless systems. This survey bridges the gap by providing a contemporary and comprehensive survey of DML techniques with a focus on wireless networks. Specifically, we review the latest applications of DML in power control, spectrum management, user association, and edge cloud computing. The optimality, scalability, convergence rate, computation cost, and communication overhead of DML are analyzed. We also discuss the potential adversarial attacks faced by DML applications, and describe state-of-the-art countermeasures to preserve privacy and security. Last but not least, we point out a number of key issues yet to be addressed, and collate potentially interesting and challenging topics for future research. Copyright © 2020, The Authors. All rights reserved.

关键词： Data privacy

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A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification

A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Yuting Tu Rongjin Xu Dawei Ye Liangjian Lyu C.-J. Richard Shi State Key Laboratory of ASIC and System Fudan University Shanghai 201203 China Institute of Brain-inspired Circuits and Systems (iBiCAS) Fudan University Shanghai 201203 China Department of Electrical and Computer Engineering University of Washington Seattle 98195 USA

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

This work proposes a high-speed pipelined-two-step time-to-digital converter (TDC) with a dynamic time amplification (DTA) to improve the resolution at low power. The key element of this TDC is the DTA. It samples the residual time errors as voltages held in the MOM capacitors and discharges them to generate the amplified time difference. Thanks to the dynamic time-voltage-time conversion, the DTA realizes high linearity and power efficiency, and can be employed to build a pipeline TDC architecture with high sampling frequency because of its sample and hold operation. Moreover, the DTA maintains constant gain, so only a one-time forground calibration for gain mismatch is required in this TDC. Simulations show that the TDC designed in 65 nm CMOS achieves 8-bit, 1.75 ps of time resolution, and 1 LSB INL and 1.6 LSB DNL with one-time foreground calibration at 400 MHz sampling frequency while just consuming 726 μW power, which corresponds to 18.45 fJ/Conv. FoM.

关键词： Delays Calibration Inverters Capacitors Linearity Tin

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Bayesian optimization approach for analog circuit synthesis using neural network

arXiv

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arXiv 2019年

作者： Zhang, Shuhan Lyu, Wenlong Yang, Fan Yan, Changhao Zhou, Dian Zeng, Xuan State Key Lab of ASIC & System Microelectronics Department Fudan University China Department of Electrical Engineering University of Texas Dallas United States

Bayesian optimization with Gaussian process as surrogate model has been successfully applied to analog circuit synthesis. In the traditional Gaussian process regression model, the kernel functions are defined explicitly. The computational complexity of training is O(N3), and the computation complexity of prediction is O(N2), where N is the number of training data. Gaussian process model can also be derived from a weight space view, where the original data are mapped to feature space, and the kernel function is defined as the inner product of nonlinear features. In this paper, we propose a Bayesian optimization approach for analog circuit synthesis using neural network. We use deep neural network to extract good feature representations, and then define Gaussian process using the extracted features. Model averaging method is applied to improve the quality of uncertainty prediction. Compared to Gaussian process model with explicitly defined kernel functions, the neural-network-based Gaussian process model can automatically learn a kernel function from data, which makes it possible to provide more accurate predictions and thus accelerate the follow-up optimization procedure. Also, the neural-network-based model has O(N) training time and constant prediction time. The efficiency of the proposed method has been verified by two real-world analog circuits. Copyright © 2019, The Authors. All rights reserved.

关键词： Deep neural networks

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A High Reliability 500 µW Resistance-to-Digital Interface Circuit for SnO2 Gas Sensor IoT Applications

A High Reliability 500 µW Resistance-to-Digital Interface C...

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International Conference on asic

作者： Jianguo Yang Xiaowen Li Qingting Ding Xiaoyong Xue Xiaoxin Xu Qing Luo Hangbing Lv Ming Liu Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of the Chinese Academy of Sciences China Huadong Hospital Affiliated to Fudan University Shanghai China ASIC and System State Key Laboratory School of Microelectronics Fudan University Shanghai China

A low power re-configurable ring oscillator (RO) based interface circuit for SnO 2 gas sensor is presented. The period of RO is dominated by the sampling voltage from gas sensor which is dependent on gas concentration. This proposed circuit improves the performance and power efficiency for resistive sensors. The interface circuit is implemented in 0.18 μm logic process with an area of 4000 μm 2 and 0.5 mW power consumption. The SnO 2 thin films deposited on a micro hotplate machined by a MEMS process and is finally integrated with the interface chip in the form of a multi-chip package. Detection of Sub-ppm-Level ethanol gas has been demonstrated, the total power consumption of the sensor is less than 25 mW, which is suitable for IoT gas detection applications.

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A dual-gate MoS2 photodetector based on interface coupling effect

arXiv

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arXiv 2019年

作者： Liao, Fuyou Chen, Xinyu Wang, Yin Zhang, Xinzhi Zhu, Hao Chen, Lin Sun, Qinging Zhou, Peng Zhang, David Wei Bao, Wenzhong Deng, Jianan Liu, Jian Wan, Jing Hu, Weida Wang, Jianlu Zhou, Jing State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai200433 China State Key Laboratory of ASIC and System School of Information Science and Technology Fudan University Shanghai200433 China Shanghai Institute of Technical Physics Chinese Academy of Sciences Shanghai200083 China

Two-dimensional (2D) transition metal dichalcogenides (TMDs) based photodetectors have shown great potential for the next generation optoelectronics. However, most of the reported MoS2 photodetectors function under the photogating effect originated from the charge-trap mechanism, which is difficult for quantitative control. Such devices generally suffer from a poor compromise between response speed and responsivity (R) and large dark current. Here, a dual-gated (DG) MoS2 phototransistor operating based on the interface coupling effect (ICE) is demonstrated. By simultaneously applying a negative top-gate voltage (VTG) and positive back-gate voltage (VBG) to the MoS2 channel, the photo-generated holes can be effectively trapped in the depleted region under TG. An ultrahigh R of ~105 A/W and detectivity (D*) of ~1014 Jones have been achieved in several devices with different thickness under Pin of 53 μW/cm2 at VTG=-5 V. Moreover, the response time of the DG phototransistor can also be modulated based on the ICE. Based on these systematic measurements of MoS2 DG phototransistors, the results show that the ICE plays an important role in the modulation of photoelectric performances. Our results also pave the way for the future optoelectrical application of 2D TMDs materials and prompt for further investigation in the DG structured phototransistors. Copyright © 2019, The Authors. All rights reserved.

关键词： Molybdenum compounds

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An FPGA-based log-structure Flash memory system for space exploration

An FPGA-based log-structure Flash memory system for space ex...

引用

International Conference on asic

作者： Huanlin Luo Yunbo Liu Hai Ren Tiantian Zhang Jian Wang Jinmei Lai State Key Laboratory of ASIC&System Fudan University Shanghai China Chengdu Sino Microelectronics Technology Co. Ltd Chengdu China

In space exploration, the flash memory system on the detector needs to retrieve the recorded data and transmit it to the Earth. In order to make better use of valuable transmission time, researchers hope that the system has more accurate retrieval capabilities. In previous space-borne flash memory system designs, the indexing accuracy of the system was limited by the limited RAM capacity. In this paper, we propose an FPGA-based system design method. This method uses a mechanism of the log structure to manage the flash to save RAM capacity. It can achieve very small data granularity, and each data particle has expandable index information, which improves the system index accuracy with limited RAM capacity. The experimental results show that the proposed system implements a 512Gb flash memory system with page-scale data granularity. It only requires 2.7Mb of RAM capacity overhead for indexing. The system has an average write rate of 329.3 Mbps and an average index latency of 39.3 us.

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Low-Dropout Regulator design with a simple structure for good high frequency PSRR performance based on Bandgap Circuit

Low-Dropout Regulator design with a simple structure for goo...

引用

International Conference on asic

作者： Xiaozhi Kang Xiaoxu Kang Zijian Zhao Jingxiu Ding Yi Hu Dapeng Xu Qingqing Sun David Wei Zhang State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China Shanghai IC R&D Center Shanghai China

This paper describes an op-amp free low-dropout regulator with a high PSRR over a broad frequency range. The design merges the high PSRR bandgap and LDO without op-amp involved and thus greatly reduces the silicon area. As no high impedence node engaged in the circuit, it is easy to achieve a good high frequency PSRR performance by using a locally regulated supply voltage. The op-amp free LDO is then developed by embedding replica technique in the bandgap. The circuit is evaluated with HHGrace 0.35μm CMOS technology. It generates a reference voltage of 1.152V and has a temperature coefficient of 0.01mV/K at 27C. LDO has a PSRR of -96dB at DC and still -48.5dB at 1MHz.

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Graphene Top-gated Mos2 Phototransistors

Graphene Top-gated Mos2 Phototransistors

引用

International Conference on asic

作者： Yaochen Sheng Xinyu Chen Fuyou Liao Jianan Deng Jing Wan Wenzhong Bao State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China School of Information Science and Engineering Fudan University Shanghai China

MoS 2 phototransistor has been widely investigated for its high sensitivity to light ranging from visible to near-infrared owing to the layer-dependent bandgap of MoS 2 . However, most of the devices in the previous studies employed a back-gate device structure, which limits its future practical application. Here, we take advantage of the high transparency of atomically thin graphene membrane to propose a top-gate phototransistor structure, in which the graphene acts as the top-gate electrode. Such MoS 2 photodetector exhibits ultrahigh responsivity reaching 1.4×10 5 AW -1 under the 550 nm incident light. The spectral response is also studied under the illumination of wavelength from 300 nm to 1000 nm. Other factors correlated with the lifetime of photogenerated carriers, including source-drain bias, gate bias, incident light intensity, are also systematically investigated.

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A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key

A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mi...

引用

IEEE Asian Conference on Solid-state Circuits (ASSCC)

作者： Xiaoyong Xue Jianguo Yang Yuejun Zhang Mingyu Wang Hangbing Lv Xiaoyang Zeng Ming Liu ASIC and System State Key Laboratory School of Microelectronics Fudan University China Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of the Chinese Academy of Sciences China School of Electrical Engineering and Computer Science Ningbo University Ningbo China

ISBN: (数字)9781728151069

ISBN: (纸本)9781728151076

Reliability and cost efficiency are of utmost importance for cryptographic key generation and storage in IoT applications. This paper presents a 2T2R RRAM PUF scheme with assisting circuit techniques for dense and reliable cryptographic key generation in 28nm logic process. The set time mismatch in two adjacent RRAM devices is exploited for PUF output with better tolerance against PVTA variations. Array architecture featuring interleaved cell mirroring improves the randomness by eliminating the systematic deviation. Self-adaptive splitting with current limiter eliminates the negative effect of mismatch in the peripheral circuits and suppresses the undue duration of large operation current. Silicon data demonstrates our RRAM PUF passes NIST test with intrachip Hamming distance (HD) of 0, inter-chip HD of 0.496 and bit error rate of -5@0-120 °C. The cell size of 2T2R PUF is 0.54 μm 2 and can be reduced when the selector is shared or the RRAM set/reset voltages are optimized below the core supply voltage.

关键词： Computer architecture Microprocessors Resistance systematics Bit error rate Cryptography Current limiters

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