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2018 IEEE MTT-S International Wireless Symposium, IWS 2018

作者： Liu, Yangzi Li, Tong Ma, Lei Yin, Yun Xu, Hongtao Yan, Na Min, Hao Department of Microelectronics State Key Laboratory of ASIC and System Fudan University No.825 Zhang-heng Road Pudong New District Shanghai201203 China

ISBN: (纸本)9781538663462

This paper presents a multimode baseband signal processing circuit of a digital polar transmitter for IoT applications. In order to support 802.11ah and NB-IoT standards with different signal bandwidths and wide frequency span, the asynchronous design is introduced to align different sampling clocks. Half-band filters are optimized through three aspects to reduce die area and power consumption. Moreover, digital pre-distortion technique is employed to successfully linearize the system. This chip performs frequency up-sampling, filtering operations, CORDIC, digital pre-distortion (DPD) to push image far way and improve signal-to-noise ratio (SNR). © 2018 IEEE.

关键词： Signal to noise ratio

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High Conductance Margin for Efficient Neuromorphic Computing Enabled by Stacking Nonvolatile van der Waals Transistors

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Physical Review Applied 2021年第4期16卷 044049-044049页

作者： Liping Xu (徐丽萍) Hao Xiong (熊浩) Zhichao Fu (付志超) Menghan Deng (邓梦晗) Shuiyuan Wang (王水源) Jinzhong Zhang (张金中) Liyan Shang (商丽燕) Kai Jiang (姜凯) Yawei Li (李亚巍) Liangqing Zhu (朱亮清) Liang He Zhigao Hu (胡志高) Junhao Chu (褚君浩) Technical Center for Multifunctional Magneto-Optical Spectroscopy (Shanghai) Engineering Research Center of Nanophotonics & Advanced Instrument (Ministry of Education) Department of Materials School of Physics and Electronic Science East China Normal University Shanghai 200241 China Center for Advanced Electronic Materials and Devices School of Electronic Information and Electrical Engineering Shanghai Jiao Tong University Shanghai 200240 China School of Computer Science and Technology East China Normal University Shanghai 200062 China ASIC & System State Key Laboratory School of Microelectronics Fudan University Shanghai 200433 China Collaborative Innovation Center of Extreme Optics Shanxi University Taiyuan Shanxi 030006 China Shanghai Institute of Intelligent Electronics & Systems Fudan University Shanghai 200433 China

High-performance artificial synaptic devices are key building blocks for developing efficient neuromorphic computing systems. However, the nonlinear and asymmetric weight update of existing devices has restricted their practical applications. Herein, floating gate nonvolatile memory (FG NVM) devices based on two-dimensional (2D) HfS2/h-BN/FG-graphene heterostructures have been designed and investigated as multifunctional NVM and artificial optoelectronic synapses. Benefiting from the FG architecture, the HfS2-based NVM device exhibits competitive performances, such as a high on:off ratio (>105), large memory window (approximately 100 V), excellent charge retention ability (>104s), and robust durability (>103 cycles). Notably, the artificial optoelectronic synapses based on HfS2 FG NVM show an impressive large conductance margin and good linearity, owing to the ultrahigh photoresponsivity and photogain of HfS2. The energy consumption of per spike in our artificial synapse is as low as 0.2 pJ. Therefore, a high recognition accuracy up to 91.5% of the artificial neural network on the basis of our HfS2-based optoelectronic synapse at the system level has been achieved, which is superior to other reported 2D artificial optoelectronic synapses. This work paves the way forward for all 2D material-based memory for developing efficient optogenetics-inspired neuromorphic computing in brain-inspired intelligent systems.

关键词： Electrical conductivity Optoelectronics Synapses 2-dimensional systems Artificial neural networks Transistors Transition metal dichalcogenides Lithography

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Clock-Aware Placement for Large-Scale Heterogeneous FPGAs

Clock-Aware Placement for Large-Scale Heterogeneous FPGAs

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作者： Chen, Jianli Lin, Zhifeng Kuo, Yun-Chih Huang, Chau-Chin Chang, Yao-Wen Chen, Shih-Chun Chiang, Chun-Han Kuo, Sy-Yen State Key Laboratory of Asic and System Fudan University Shanghai China College of Mathematics and Computer Science Fuzhou University Fuzhou China MediaTek Hsinchu Taiwan Synopsys Hsinchu Taiwan Department of Electrical Engineering Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou350000 China Department of Computer Science and Information Engineering National Taiwan University Taipei106 Taiwan

A modern field-programmable gate array (FPGA) often contains an asic-like clocking architecture which is crucial to achieve better skew and performance. Existing conventional FPGA placement algorithms seldom consider clocking resources, and thus may lead to clock routing failures. To address the special FPGA clocking architecture, this article presents an effective clock-aware placement algorithm for large-scale heterogeneous FPGAs. Our algorithm consists of four major technologies: 1) a combinatorial clock fence region method to effectively reduce the overuse of clocking resources;2) a smoothed heterogeneous density function to lead heterogeneous blocks to desired sites and a coordinate transformation technique to facilitate CLB cell spreading;3) a heterogeneous force modulation algorithm to stabilize placement movement and a hierarchical contraction technique to remedy an insufficiency of the multilevel placement framework;and 4) a two-level clock-aware packing and legalization scheme to generate an optimized, clocking-violation-free placement. We evaluate our results based on the ISPD 2017 Clock-Aware Placement Contest benchmark suite. Compared with the state-of-the-art placers, the experimental results show that our algorithm achieves the best-routed wirelength. © 1982-2012 IEEE.

关键词： Clocks

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ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set

ALSRAC: Approximate Logic Synthesis by Resubstitution with A...

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Design Automation Conference

作者： Chang Meng Weikang Qian Alan Mishchenko University of Michigan-Shanghai Jiao Tong University Joint Institute Shanghai Jiao Tong University Shanghai China MoE Key Laboratory of Artificial Intelligence Shanghai Jiao Tong University Shanghai China State Key Laboratory of ASIC & System Fudan University Shanghai China Department of Electrical Engineering and Computer Sciences University of California Berkeley USA

ISBN: (数字)9781728110851

ISBN: (纸本)9781728158020

Approximate computing is an emerging design technique for error-resilient applications. It improves circuit area, power, and delay at the cost of introducing some errors. Approximate logic synthesis (ALS) is an automatic process to produce approximate circuits. This paper proposes approximate resubstitution with approximate care set and uses it to build a simulation-based ALS flow. The experimental results demonstrate that the proposed method saves 7%-18% area compared to state-of-the-art methods. The code of ALSRAC is made open-source.

关键词： Error analysis Logic gates Delays Measurement uncertainty Integrated circuit modeling Erbium

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Improved Polarization Retention of BiFeO3 Thin Films Using GdScO3(110)Substrates

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Chinese Physics Letters 2017年第2期34卷 104-107页

作者： Shuai-Qi Xu Yan Zhang Hui-Zhen Guo Wen-Ping Geng Zi-Long Bai An-Quan Jiang State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433

Epitaxial ferroelectric one direction over the thin fihns on single-crystal substrates generally show a preferred domain orientation in other in demonstration of a poor polarization retention. This behavior will affect their application in nonvolatile ferroelectric random access memories where bipolar polarization states are used to store the logic 0 and 1 data. Here the retention characteristics of BiFe03 thin films with Srftu03 bottom electrodes on both GdSc03 （110） and SrTiO3 （100） substrates are studied and compared, and the results of piezoresponse force microscopy provide a long time retention property of the films on two substrates. It is found that bismuth ferrite thin films grown on GdScO3 substrates show no preferred domain variants in comparison with the preferred downward polarization orientation toward bottom electrodes on SrTi03 substrates. Tile retention test from a positive-up domain to a negative-down domain using a signal generator and an oscilloscope coincidentally shows bistable polarization states on the GdSeOa substrate over a measuring time of 500s, unlike the preferred domain orientation on SrTi03, where more than 65~o of upward domains disappear after 1 s. In addition, different sizes of domains have been written and read by using the scanning tip of piezoresponse force microscopy, where the polarization can stabilize over one month. This study paves one route to improve the polarization retention property through the optimization of the lattice-mismatched stresses between films and substrates.

关键词： BFO GSO Improved Polarization Retention of BiFeO3 Thin Films Using GdScO3 Substrates SRO 110

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Erratum: Assessment of 180 nm double SOI technology for analog front-end design with back-gate voltage

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Journal of Instrumentation 2024年第10期19卷 E10001-E10001页

作者： Y. Li F. Liu B. Lu Z. Li S. Chen C. Zhang H. Zhu X. Yao J. Bu J. Wan Y. Xu S. Cristoloveanu B. Li J. Luo T. Ye Institute of Microelectronics of the Chinese Academy of Sciences 3 Beitucheng West Road Beijing 100029 China University of Chinese Academy of Sciences 19 A Yuquan Road Beijing 100049 China Key Laboratory of Science and Technology on Silicon Devices Chinese Academy of Sciences 3 Beitucheng West Road Beijing 100029 China State Key Laboratory of Particle Detection and Electronics of China 19 B Yuquan Road Beijing 100049 China Institute of High Energy Physics Chinese Academy of Science 19 B Yuquan Road Beijing 100049 China State key lab of ASIC and System Fudan University No. 825 Zhangheng Road Shanghai 200433 China College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunication No. 9 Wenyuan Road Nanjing 210023 China Guangdong Greater Bay Area Institute of Integrated Circuit and System No. 136 Kaiyuan Avenue Guangzhou 510535 China

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Complementary Memory Cell Based on Field-Programmable Ferroelectric Diode for Ultra-Low Power Current-SA Free BNN Applications

Complementary Memory Cell Based on Field-Programmable Ferroe...

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International Electron Devices Meeting (IEDM)

作者： Qing Luo Bing Chen Rongrong Cao Xiaoyong Xue Keji Zhou Jianguo Yang Xu Zheng Haoran Yu Jie Yu Tiancheng Gong Xiaoxin Xu Peng Yuan Xiaoyan Li Lu Tai Qi Liu Hangbing Lv Ming Liu Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of the Chinese Academy of Sciences Beijing China The College of Information Science and Electronic Engineering Zhejiang University Hangzhou China State Key Laboratory of ASIC and System Fudan University Shanghai China

In this work, we proposed a complementary memory cell with 2T4D XNOR structure for computing in memory (CIM) applications. Firstly, a field-programmable diode (FPD) was demonstrated with a W/Hf 0 5Zr 0 5O 2 (HZO)/W structure. After analyzing the mechanism of FPD device, a 1T2D structure was proposed for voltage-output memory application featuring stable voltage ratio (~0.9 V), read disturbance immunity (>10 9 ) and ultra-low leakage current (2) and superior efficiency (387 TOPS/W).

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Reward-modulated spike-timing-dependent plasticity in van der Waals ferroelectric memtransistor for robotic recognition and tracking

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Science Bulletin 2025年

作者： Yi Cao Jinhao Liang Tao Liu Weihui Sang Yang Gan Honghong Li Yue Wang Zheng Ren Yuan Yu Zhou Xin Yukang Chen Xumeng Zhang Du Xiang Qi Liu State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai 200433 China School of Microelectronics Fudan University Shanghai 200433 China Shanghai Frontiers Science Research Base of Intelligent Optoelectronics and Perception Institute of Optoelectronics and Department of Materials Science Fudan University Shanghai 200433 China Zhangjiang Fudan International Innovation Center Fudan University Shanghai 200433 China

Reward-modulated spike-timing-dependent plasticity (R-STDP) is a promising biomimetic learning rule in neuromorphic intelligent systems for implementing tasks in variable environments. Nevertheless, realizing R-STDP in a single synaptic device for building compact and energy-efficient neuromorphic systems remains challenging. Here, we report a two-dimensional ferroelectric memtransistor to emulate the R-STDP learning rule by effectively reconfiguring the STDP and anti-STDP. The thermionic emission and tunneling behavior of charges at the ferroelectric interface can be regulated via vertical electric field in a multi-terminal manner, allowing for controllable polarization reversal of synaptic plasticity and transition between STDP and anti-STDP. This enables faithful realization of the R-STDP feature in a single device with energy consumption of ∼1.3 nJ (the lowest known to date), approximately 10 6 times lower than that of its complementary metal-oxide-semiconductor (CMOS) counterpart. By leveraging the synaptic characteristics in the hardware device, we construct spiking neural networks (SNNs) trained with R-STDP to perform robotic recognition and tracking tasks. The SNN achieves 95.1% accuracy on the MNIST dataset using only 8000 parameters, and faster convergence speed requiring only one data batch with 100% inference in the few-shot learning task. Moreover, a robotic arm motion control system configured with R-STDP exhibits 85.5% success rate in tracking both the static and moving targets, illustrating its outstanding adaptability to the dynamic environments. This work provides a potential hardware building block to support compact neuromorphic systems for the application of interactive artificial intelligence agents.

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MoS2dual-gate transistors with electrostatically doped contacts

arXiv

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arXiv 2019年

作者： Liao, Fuyou Sheng, Yaocheng Guo, Zhongxun Tang, Hongwei Wang, Yin Zong, Lingyi Chen, Xinyu Riaud, Antoine Zhu, Jiahe Xie, Yufeng Chen, Lin Zhu, Hao Sun, Qingqing Zhou, Peng Jiang, Xiangwei Wan, Jing Bao, Wenzhong Zhang, David Wei State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai200433 China State Key Laboratory of ASIC and System School of Information Science and Engineering Fudan University Shanghai200433 China School of Electronic Science and Engineering Nanjing University Nanjing210093 China Institute of Semiconductors Chinese Academy of Sciences Beijing100083 China

Two-dimensional (2D) transition metal dichalcogenides (TMDs) such as molybdenum disulfide (MoS2) have been intensively investigated because of their exclusive physical properties for advanced electronics and optoelectronics. In the present work, we study the MoS2transistor based on a novel tri-gate device architecture, with dual-gate (Dual-G) in the channel and the buried side-gate (Side-G) for the source/drain regions. All gates can be independently controlled without interference. For a MoS2sheet with a thickness of 3.6 nm, the Schottky barrier (SB) and non-overlapped channel region can be effectively tuned by electrostatically doping the source/drain regions with Side-G. Thus, the extrinsic resistance can be effectively lowered, and a boost of the ON-state current can be achieved. Meanwhile, the channel control remains efficient under the Dual-G mode, with an ON-OFF current ratio of 3×107and subthreshold swing of 83 mV/decade. The corresponding band diagram is also discussed to illustrate the device operation mechanism. This novel device structure opens up a new way toward fabrication of high-performance devices based on 2D-TMDs. Copyright © 2019, The Authors. All rights reserved.

关键词： Sulfur compounds

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Towards Efficient Deep Neural Network Training by FPGA-Based Batch-Level Parallelism

Towards Efficient Deep Neural Network Training by FPGA-Based...

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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Cheng Luo Man-Kit Sit Hongxiang Fan Shuanglong Liu Wayne Luk Ce Guo State Key Laboratory of ASIC and System Fudan University Shanghai China Department of Computing Imperial College London London United Kingdom

Training Deep Neural Networks (DNNs) requires a significant amount of time and resources to obtain acceptable results, which severely limits its deployment in resource-limited platforms. This paper proposes DarkFPGA, a novel customizable framework to efficiently accelerate the entire DNN training on a single FPGA platform. First, we explore batch-level parallelism to enable efficient training on FPGAs. Second, we devise a novel hardware architecture optimised by a batch-oriented data pattern and tiling techniques to effectively exploit parallelism. Moreover, an analytical model is developed to determine the optimal design parameters for the DarkFPGA accelerator with respect to a specific network specification and FPGA resource constraints. Our results show that the accelerator is able to perform about 11 times faster than CPU training and about a third of the energy consumption than GPU training using 8-bit integers for training VGG-like networks on the CIFAR dataset for the Maxeler MAX5 platform.

关键词： Training Field programmable gate arrays Parallel processing Kernel Acceleration Computer architecture Random access memory

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