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Recent Advances in Electrochemical-Based Silicon Production Technologies with Reduced Carbon Emission

Research 2024年第1期2023卷 209-236页

作者： Feng Tian Zhongya Pang Shen Hu Xueqiang Zhang Fei Wang Wei Nie Xuewen Xia Guangshi Li Hsien-Yi Hsu Qian Xu Xingli Zou Li Ji Xionggang Lu State Key Laboratory of Advanced Special Steel&Shanghai Key Laboratory of Advanced Ferrometallurgy&School of Materials Science and Engineering Shanghai University99#Shangda RoadShanghai 200444China Center for Hydrogen Metallurgy Technology Shanghai UniversityShanghai 200444China State Key Laboratory of ASIC and System School of MicroelectronicsFudan University220#Handan RoadShanghai 200433China School of Energy and Environment Department of Materials Science and EngineeringCity University of Hong KongKowloon TongHong KongChina

Sustainable and low-carbon-emission silicon production is currently one of the main focuses for the metallurgical and materials science ***,considered a promising strategy,has been explored to produce silicon due to prominent advantages:(a)high electricity utilization efficiency;(b)low-cost silica as a raw material;and(c)tunable morphologies and structures,including films,nanowires,and *** review begins with a summary of early research on the extraction of silicon by *** has been placed on the electro-deoxidation and dissolution–electrodeposition of silica in chloride molten salts since the 21st century,including the basic reaction mechanisms,the fabrication of photoactive Si films for solar cells,the design and production of nanoSi and various silicon components for energy conversion,as well as storage ***,the feasibility of silicon electrodeposition in room-temperature ionic liquids and its unique opportunities are *** this basis,the challenges and future research directions for silicon electrochemical production strategies are proposed and discussed,which are essential to achieve large-scale sustainable production of silicon by electrochemistry.

关键词： directions electrodeposition electricity

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A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter 44

A Self Bias-flip Piezoelectric Energy Harvester Array withou...

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44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023

作者： Li, Zhen Chen, Zhiyuan Law, Man-Kay Du, Sijun Cheng, Xu Zeng, Xiaoyang Han, Jun Fudan University State Key Laboratory of Asic and System Shanghai China University of Macau State Key Laboratory of Analog and Mixed-Signal Vlsi China Delft University of Technology Department of Microelectronics Delft Netherlands

ISBN: (纸本)9798350399486

With the advent of the lnternet-of-Things (1oT) era, sensor nodes are required in almost all fields to achieve a better interaction between humans and the environment. Piezoelectric energy harvester (PEH), which exhibits an equivalent electrical model of an AC current source /P in parallel with the inherent capacitor CP, is a promising technology to resolve the energy problem of such sensor nodes. Recently, inductor-based rectifiers, capacitor-based rectifiers and hybrid rectifiers have been proposed to improve the energy extraction efficiency of PEH devices [1]-[5]. However, these structures all require the aid of additional capacitors or inductors to achieve bias-flip operation, as illustrated in Fig. 1. These extra passive devices are typically large, which can be a major bottleneck in system-volumeconstrained applications such as MEMS [4]. In response to the above problem, this work proposes a novel 8-phase self bias-flip PEH interface with charge recycling and reusing (SBFRR). By using the C P of 4 PEHs as flipping capacitors, this scheme achieves a high voltage flipping efficiency without using extra energy reservoirs. The 4 C P can also serve as flying capacitors to achieve switched-PEH DC-DC (SPDC) conversion for MPPT, while maintaining a MOPIR of >3.5× with a PEH input voltage (Vp) from 0. 78Vto4.9V. © 2023 IEEE.

关键词： Sensor nodes

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Ferroelectric artificial synapse for neuromorphic computing and flexible applications

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Fundamental Research 2023年第6期3卷 960-966页

作者： Qing-Xuan Li Yi-Lun Liu Yuan-Yuan Cao Tian-Yu Wang Hao Zhu Li Ji Wen-Jun Liu Qing-Qing Sun David Wei Zhang Lin Chen State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China National Integrated Circuit Innovation Center No.825 Zhangheng RoadShanghai 201203China

Research of artificial synapses is increasing in popularity with the development of bioelectronics and the appearance of wearable *** the high-temperature treatment process of inorganic materials is not compatible with flexible substrates,organic ferroelectric materials that are easier to process have emerged as *** organic synaptic device based on P(VDF-TrFE)was prepared in this *** device showed reliable P/E endurance over 104 cycles and a data storage retention capability at 80℃ over 104 ***,it possessed excellent synaptic functions,including short-term/long-term synaptic plasticity and spike-timing-dependent *** addition,the ferroelectric performance of the device remained stable even under bending(7 mm bending radius)or after 500 bending *** work shows that low-temperature processed organic ferroelectric materials can provide new ideas for the future development of wearable electronics and flexible artificial synapses.

关键词： Organic artificial synapse Neuromorphic computing Synaptic devices Wearable electronics Ferroelectric

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Knowledge-based neural network SPICE modeling for MOSFETs and its application on 2D material field-effect transistors

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Science China(Information Sciences) 2023年第2期66卷 227-236页

作者： Guodong QI Xinyu CHEN Guangxi HU Peng ZHOU Wenzhong BAO Ye LU State Key Laboratory of ASIC and System School of Information Science and TechnologyFudan University State Key Laboratory of ASIC and System School of Microelectronics Fudan University Zhangjiang Fudan International Innovation Center Fudan University

As the traditional scaling of silicon metal-oxide-semiconductor field-effect transistors（MOSFETs） reaches its physical limit, research efforts on novel semiconductor devices are increasingly desired. To enable the joint optimization of early-stage circuit design and process of novel devices, the rapid creation of an accurate compact model of these devices with the capability to cover process variations is required. In this work, a knowledge-based neural network（KNN） modeling method is proposed. This method separates the geometrical variables from the other input variables of the device, where the geometrical variables are modeled with physics-based analytical equations, while the remaining part is modeled by an artificial neural network. The KNN model takes advantage of the automated numerical fitting capability of the neural network and the geometrical scalability from device physics. The created KNN model is first validated with silicon MOSFET data from the industry standard BSIM6 and shows more than 20% accuracy improvement as compared with the traditional neural network model. Furthermore, MoS2field-effect transistors and circuits,such as ring oscillators, standard cells, and logic functional circuits, are experimentally fabricated for model verification. The results show that the KNN model is capable of predicting the electrical characteristics of devices beyond the measurement geometry and facilitates the accurate simulations of statistical circuits with respect to experimental data. This work paves the way for future circuit designs and simulations of novel semiconductor devices.

关键词： knowledge-based neural network MOSFET 2D material FETs Monte Carlo simulations circuit benchmark

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Flexible 3D memristor array for binary storage and multi-states neuromorphic computing applications

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InfoMat 2021年第2期3卷 212-221页

作者： Tian-Yu Wang Jia-Lin Meng Lin Chen Hao Zhu Qing-Qing Sun Shi-Jin Ding Wen-Zhong Bao David Wei Zhang State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghaiChina

The demand of flexible neuromorphic computing electronics is increasing with the rapid development of wearable artificial intelligent *** flexible resistive random-access memory(RRAM)is one excellent candidate of highdensity storage ***,due to the limitations of fabrication process,materials system and device structure,it is difficult to prepare flexible 3D highdensity network for neuromorphic *** this paper,a 3D flexible memristors network is developed via low-temperature atomic layer deposition(ALD)at 130C,with potential of extending to various flexible *** typical bipolar switching characteristics are verified in RRAM units of 3D network,including first,second and third *** binary storage,the multibit storage in single unit is demonstrated and the storage density is further *** a connection link between binary storage and brain-inspired neuromorphic computing,the multibit storage capability paves the way for the tunable synaptic plasticity,for example,long-term potentiation/depression(LTP/LTD).The 3D memristors network successfully mimicked the typical neuromorphic functionality and realized ultra-multi conductance states modulation under 600 *** robust mechanical flexibility is further demonstrated via LTP/LTD emulation under bending states(radius=10 mm).The 3D flexible memristors network shows significant potential of applications in high-performance,high-density and reliable wearable neuromorphic computing system.

关键词： 3D crossbar brain-inspired computing flexible memory low-temperature ALD multilevel storage

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Integrating 2D layered materials with 3D bulk materials as van der Waals heterostructures for photodetections:Current status and perspectives

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InfoMat 2023年第10期5卷 1-31页

作者： Weijie Liu Yiye Yu Meng Peng Zhihua Zheng Pengcheng Jian Yang Wang Yuanchen Zou Yongming Zhao Fang Wang Feng Wu Changqing Chen Jiangnan Dai Peng Wang Weida Hu Wuhan National Laboratory for Optoelectronics Huazhong University of Science and TechnologyWuhanthe People's Republic of China State Key Laboratory of Infrared Science and Technology Shanghai Institute of Technical PhysicsChinese Academy of SciencesShanghaithePeople's Republic of China State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghaithe People's Republic of China

In the last decade,two-dimensional layered materials(2DLMs)have been drawing extensive attentions due to their unique properties,such as absence of surface dangling bonds,thickness-dependent bandgap,high absorption coeffi-cient,large specific surface area,and so *** the high-quality growth and transfer of wafer-scale 2DLMs films is still a great challenge for the commerciali-zation of pure 2DLMs-based ***,the material growth and device fabrication technologies of three-dimensional(3D)semiconductors photodetectors tend to be gradually ***,the further improvement of the photodetection performance is limited by the difficult heterogeneous inte-gration or the inferior crystal quality via ***,2D/3D van der Waals heterostructures(vdWH)combine the advantages of the two types of materials simultaneously,which may provide a new platform for developing high-performance optoelectronic ***,we first discuss the unique advantages of 2D/3D vdWH for the future development of photodetection field and simply introduce the structure categories,working mechanisms,and the typical fabrication methods of 2D/3D vdWH ***,we outline the recent progress on 2D/3D vdWH-based photodetection devices integrating 2DLMs with the traditional 3D semiconductor materials,including Si,Ge,GaAs,AlGaN,SiC,and so ***,we highlight the current challenges and pros-pects of heterointegrating 2DLMs with traditional 3D semiconductors toward photodetection applications.

关键词： photodetectors three-dimensional semiconductors two-dimensional layered materials vander Waals heterostructures

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Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity

Adaptable Approximate Multiplier Design Based on Input Distr...

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作者： Li, Zhen Zheng, Su Zhang, Jide Lu, Yao Gao, Jingbo Tao, Jun Wang, Lingli Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai201203 China

Approximate computing is an efficient approach to reduce the design complexity for error-resilient applications. Multipliers are key arithmetic units in many applications, such as deep neural networks (DNNs) and digital signal processing (DSP) systems. In this article, an open-source adaptable approximate multiplier design driven by input distribution and polarity is proposed to generate optimized approximate multipliers to trade off between the application-level performance and the hardware cost. The proposed method minimizes the average square of the absolute error of an approximate multiplier according to the probability distributions of operands extracted from the target application with consideration of input polarity, achieving low hardware cost and negligible application-level performance loss. The proposed method can generate unsigned multipliers (or signed multipliers) based on the Braun multiplier (or Baugh-Wooley multiplier). To demonstrate the effectiveness of the method, three different-scale quantized DNNs, including LeNet, AlexNet, and VGG16 with 8 × 8 unsigned multiplication and an adaptive least mean square (LMS)-based finite impulse response (FIR) filter with 16 × 16 fixed-point signed multiplication, are evaluated. In the DNN training process, a noise training technique is adopted to reduce the accuracy loss due to the approximation. When compared to the state-of-the-art approximate multipliers, the generated multipliers can achieve up to 26.4% and 27.1% product of power, delay, and area gains with negligible application-level performance loss in VGG16 and FIR applications, respectively. © 1993-2012 IEEE.

关键词： Impulse response

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Automated Design Space Exploration of Coarse-Grained Reconfigurable Architecture via Bayesian Optimization 16

Automated Design Space Exploration of Coarse-Grained Reconfi...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Kuang, Huizhen Zheng, Su Wang, Lingli Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Due to high energy efficiency, runtime reconfigurability, and low hardware cost, coarse-grained reconfigurable architecture (CGRA) is promising in many rapid-evolving applications. Nevertheless, CGRA architecture design is an extremely costly task that requires searching a vast design space. We propose a fast automated design space exploration (DSE) algorithm based on Bayesian optimization (BO) to search the design space modeled by a black-box. Experimental results show that our approach significantly outperforms simulated annealing (SA) and genetic algorithm (GA). The optimized architecture has dramatic mapping performance improvements while saving the hardware area by 36% and 12% respectively compared with the optimized architectures by GA and SA. © 2022 IEEE.

关键词： Simulated annealing

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A 250MS/s, 12 Bit Pipeline-SAR ADC Using Coarse-Fine Ring Amplifier

A 250MS/s, 12 Bit Pipeline-SAR ADC Using Coarse-Fine Ring Am...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Linghao Liu Junyan Ren Fan Ye Department of Microelectronics State Key Laboratory of ASIC and System Fudan University Shanghai China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

The ring amplifier is an energy effective choice for high performance pipeline ADC. However, sensitivity to process, supply voltage and temperature (PVT) variations and complex stability mechanism make it less practical. This brief introduces a coarse-fine ring amplifier (CFRingAmp) that allows individual designs of large-signal and small-signal processes. With a large and a smaller dead-zones switched by the self-detect-and-switch block, both stability and accuracy are well designed over corners. Furthermore, a 250MS/s, 12-bit pipeline-SAR ADC is implemented adopting the proposed CFRingAmp. Simulated in 28nm CMOS, the ADC achieves an SNDR of 64.1 dB and an SFDR of 74.9 dB over corners at Nyquist frequency while consuming 4.5mW, resulting a Walden figure-of merit (FoM) of 12.7 fJ/conversion step.

关键词： Temperature sensors Accuracy Sensitivity Simulation Voltage Switches Stability analysis Circuit stability Registers Thermal stability

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Integration of Droplet Transport and Mixing on EWOD 16

Integration of Droplet Transport and Mixing on EWOD

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Gao, Shang Rui, Xichuan Zhou, Jia Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Microdroplet transportation and mixing are indispensable functions in lab-on-chip applications. Additional components to conventional microfluidic platforms have solved the problem but with the big increase in the complexity of system integration. Here we propose an EWOD (Electrowetting on Dielectrics) design of driving electrode with a micro-barrier structure that enables the droplet mixing simultaneously along with the unidirectional transportation controlled by only two signals. The nesting asymmetrical electrodes not only provide the unidirectional driving pressure to the droplets, but also enhance the mixing of droplets by the specific micro-barrier structure through the curvilinear and fluctuating movement of the droplets. This design demonstrates a new approach to functional integration of EWOD microfluidic chips, which is of great significance in bioanalysis, especially in POCT (Point of Care Technology). © 2022 IEEE.

关键词： Drops

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