This paper reports a novel monolithic lab-on-a-chip (LOC)with an electrochemical system embedded in an electrowetting on dielectric(EWOD)microfluidic device for the first *** fabrication process is compatible with...
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This paper reports a novel monolithic lab-on-a-chip (LOC)with an electrochemical system embedded in an electrowetting on dielectric(EWOD)microfluidic device for the first *** fabrication process is compatible with IC *** chip could not only merge and transport droplets successfully,but show good electrochemical responses of glucose and glucose oxidase with the sensitivity of 0.028mA/mM and the statistic adjust R-square of 0.9549.
This paper explores two low temperature technological developments related to future n-MOSFETs using III-V semiconductors as channel materials. (1). It was found that Yb-GaAs Schottky contact with RTA at 500°C fo...
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This paper explores two low temperature technological developments related to future n-MOSFETs using III-V semiconductors as channel materials. (1). It was found that Yb-GaAs Schottky contact with RTA at 500°C for 30s has good rectifying characteristics, low effective electron barrier height, low sheet resistivity, atomically sharp junction with GaAs. These properties are suitable for source/drain (S/D) formation in GaAs n-MOSFETs. (2). GaAs MOS capacitors were fabricated by E-gun deposition of LaAlO 3 (LAO) dielectric and PVD deposition of TaN electrode. The capacitors with well-behaved CV characteristics with EOT=3nm, gate leakage currents 7.5×10 -3 A/cm 2 for 500°C RTA treated samples at V fb -1V were achieved.
We verify the domain sideway motion around the peripheral regions of the crossed capacitors of top and bottom electrode bars without electrode *** avoid the crosstalk problem between adjacent memory cells,the safe dis...
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We verify the domain sideway motion around the peripheral regions of the crossed capacitors of top and bottom electrode bars without electrode *** avoid the crosstalk problem between adjacent memory cells,the safe distance between adjacent elements of Pt/SrBi_(2)Ta_(2)O_(9)/Pt thin−film capacitors is estimated to be 0.156µ***,the fatigue of Pt/SrBi_(2)Ta_(2)O_(9)/Pt thin-film capacitors is independent of the individual memory size due to the absence of etching damage.
An attractive+ to graphene for a range of applications is graphene oxide (GO). GO is an insulator because of the hydroxyl, carboxyl, carbonyl and epoxide functional groups presenting on the basal surface or edge and b...
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ISBN:
(纸本)9781467328715
An attractive+ to graphene for a range of applications is graphene oxide (GO). GO is an insulator because of the hydroxyl, carboxyl, carbonyl and epoxide functional groups presenting on the basal surface or edge and becomes a semiconductor or semimetal as it is reduced back toward graphene. Here we demonstrate that graphene oxide can be reversibly reduced and oxidized in nanometer-scale by applying bias voltages by the nano-tip of conductive atomic force microscopy system. The low resistance state (LRS) when reduced and a high resistance state (HRS) when oxidized can be achieved under the opposite applied bias direction. The LRS (around 10 KΩ and HRS (around 40 M Ω) were stable for more than 10 3 s, and no obvious degradation was observed during the tests. Threshold voltages for reduction and oxidation, which can be considered as the set and reset voltages is around -6.5 V and +7 V, respectively. It is shown that the hydrogen (H+) ions and hydroxyl ions (OH-) dissociated from the water meniscus formed between the tip and GO in ambient condition at room temperature plays an essential role in the resistive memory switching. It is also found that the negative bias is responsible for the reduction, which is related the transition from HRS to LRS, and the positive bias is responsible for the oxidation, which is related the transition from LRS to HRS, respectively. Raman spectroscopy and X-ray photoelectron spectroscopy is performed to confirm this resistive memory switching behaviors.
Microfluidic channels on the size of tens of microns are being developed for use in a variety of applications such as microreactors, DNA analysis, and micro total analysis systems. Among the fabrication techniques for...
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The finite element method (FEM) is employed to investigate the solder crack mechanism in wafer level chip scale packaging (WLCSP). The location of the initial crack is calculated and is compared to the experimental on...
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The finite element method (FEM) is employed to investigate the solder crack mechanism in wafer level chip scale packaging (WLCSP). The location of the initial crack is calculated and is compared to the experimental one. Moreover, the impact of the following three aspects, e.g. under-bump metallurgy (UBM) materials, solder alloy, and the thickness of the UBM layers on the initial crack growth in solder is investigated by calculating J-integral, respectively, which reflects the possibility of crack growth. It is concluded that the J-integral values in 96.5Sn3.5Ag solder and the Au-Ni-Cu-Ti UBM material are smaller than other cases.
μ-law companding and de-companding, which enlarges small signals and compresses large signals, can work successfully in the CO-OFDM transmission system, and μ=1 is the optimal companding coefficient for PAPR reduction.
μ-law companding and de-companding, which enlarges small signals and compresses large signals, can work successfully in the CO-OFDM transmission system, and μ=1 is the optimal companding coefficient for PAPR reduction.
A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk p...
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A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB (ENOB = 9.69 bits) and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.
This paper presents a novel hardware-oriented decoding algorithm in the log-domain for non-binary LDPC codes over GF(2 m ). As for max-log-SPA, only summations and comparisons are required in this new algorithm. Durin...
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This paper presents a novel hardware-oriented decoding algorithm in the log-domain for non-binary LDPC codes over GF(2 m ). As for max-log-SPA, only summations and comparisons are required in this new algorithm. During the vertical update, these two operations are divided into layers based on the distribution of variable vectors that satisfy the check function. The number of additions during the vertical update is reduced by a factor of approximately p-2 without a performance loss, where p is the row weight of the parity check matrix.
Hafnium silicate-based Metal Oxide Semiconductor (MOS) capacitors were fabricated by atomic layer deposition. The interface evolution of the films with forming gas annealing was investigated. It is found that most of ...
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ISBN:
(纸本)9781467324748
Hafnium silicate-based Metal Oxide Semiconductor (MOS) capacitors were fabricated by atomic layer deposition. The interface evolution of the films with forming gas annealing was investigated. It is found that most of the slow interface states were passivated through Forming Gas Annealing (FGA), and the D_(it) in the center of the band gap was estimated to be 2.3 × 10~(11) eV~(-1)cm~(-2). It is also found that interface layer can react with HfO_2 to form HfSiO_x in the process of FGA at elevated temperature, and the interface thickness was reduced to 0.4 nm after FGA at 600 ℃.
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