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Asia and South Pacific Design Automation Conference

作者： Jian Sun Yinghai Lu Hai Zhou Xuan Zeng State Key Laboratory of ASIC & System Microelectronics Department Fudan University China EECS Department Northwestern University USA

ISBN: (纸本)9781424475162

Double patterning lithography, where one-layer layout is decomposed into two masks, is believed to be inevitable for 32nm technology node of the ITRS roadmap. However, post-routing layer assignment, which decides the layout pattern on each layer, thus having great impact on double patterning related parameters, has not been explored in the merit of double patterning. In this paper, we propose a post-routing layer assignment algorithm for double patterning optimization. Our solution consists of three major phases: multi-layer assignment, single-layer double patterning, and via reduction. For phase one and three, multi-layer graph is constructed and dynamic programming is employed to solve optimization problem on this graph. In the second phase, single-layer double patterning is proved NP-hard and existing algorithm is implemented to optimize single layer double patterning problem. The proposed method is tested on CBL (Collaborative Benchmarking laboratory) benchmarks and shows great performance. In comparison with single-layer double patterning, our method achieves 73% and 27% average reduction for unresolvable conflicts and stitches respectively, with only 9% increase of via number. When double patterning is constrained on only the bottom two metal layers as in current technology, these numbers become 62%, 8% and 0.42%.

关键词： Layout Color Metals Dynamic programming Wire Heuristic algorithms Optimization

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An efficient algorithm for multi-domain clock skew scheduling

An efficient algorithm for multi-domain clock skew schedulin...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Yanling Zhi Wai-Shing Luk Hai Zhou Changhao Yan Hengliang Zhu Xuan Zeng State Key Laboratory of ASIC & System Microelectronics Department Fudan University China Department of EECS Northwestern University USA

ISBN: (纸本)9781612842080

Conventional clock skew scheduling for sequential circuits can be formulated as a minimum cycle ratio (MCR) problem, and hence can be solved effectively by methods such as Howard's algorithm. However, its application is practically limited due to the difficulties in reliably implementing a large set of arbitrary dedicated clock delays for the flip-flops. Multi-domain clock skew scheduling was proposed to tackle this impracticality by constraining the total number of clock delays. Even though this problem can be formulated as a mixed integer linear programming (MILP), it is expensive to solve optimally in general. In this paper, we show that, under mild restrictions, the underlying domain assignment problem can be formulated as a special MILP that can be solved effectively using similar techniques for the MCR problem. In particular, we design a generalized Howard's algorithm for solving this problem efficiently. We also develop a critical-cycle-oriented refinement algorithm to further improve the results. The experimental results on ISCAS89 benchmarks show both the accuracy and efficiency of our algorithm. For example, only 4.3% of the tests have larger than 1% degradation (3% in the worst case), and all the tests finish in less than 0.7 seconds on a laptop with a 2.1GHz processor.

关键词： Clocks Clustering algorithms Timing Scheduling Algorithm design and analysis Degradation Sequential circuits

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Origin of high on-state current for dopant-segregated schottky MOSFET

Origin of high on-state current for dopant-segregated schott...

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International Conference on asic

作者： Yang Tang Liu-Lin Zhong Yu-Long Jiang State Key Lab of ASIC and System Department of Microelectronics Fudan University Shanghai China

The origin of the on-state current (I on ) difference between dopant-segregated Schottky (DSS) source/drain MOSFET and conventional MOSFET with 20nm channel length is investigated by device simulation. The simulation results coincide well with the published experimental result. It is revealed that the not-fully-depleted dopant-segregated layer leads to a severe DIBL effect which contributes to the I on enhancement for DSS MOSFET.

关键词： Decision support systems Very large scale integration

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Simulation of carrier transport in quantum cascade lasers

Simulation of carrier transport in quantum cascade lasers

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2011 IEEE 9th International Conference on asic, asicON 2011

作者： Li, Yingying Ru, Guo-Ping Simon Li, Z.-M. State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai 200433 China Crosslight Software Inc. 121-3989 Henning Dr. Burnaby BC V5C 6P8 Canada

ISBN: (纸本)9781612841908

We report a simulation study of carrier transport in quantum cascade lasers (QCLs) based on non-local transport model. In this model, drift-diffusion equations are solved with modification of current density by accounting for long-range carrier transport including quantum tunneling and hot carrier transport in the device. From the simulation results of an AlInGaAs/InP QCL at different temperatures, it is found that our model shows reasonable agreement with experiments at lower temperature when carriers are well confined while substantial deviation is observed at higher temperatures when the leakage of carriers into the continuum is significant. © 2011 IEEE.

关键词： Quantum cascade lasers

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Investigation of Novel Junctionless MOSFETs for Technology Node Beyond 22 nm

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ECS Transactions 2012年第1期44卷

作者： Peng Xu Yinghua Piao Liang Ge Cheng Hu Lun Zhu Zhiwei Zhu David Wei Zhang Dongping Wu School of Microelectronics Fudan University No.220 Han Dan Road YangPu Area Shanghai Shanghai 200433 China Fudan University State Key Laboratory of ASIC and System Fudan University Handan Road 220 Room 302 Microelectronics building Fudan university Shanghai Shanghai 200433 China

In this paper, junctionless MOSFETs with un-uniformly doped source/drain and channel regions have been thoroughly investigated. Un-uniformly doped junctionless MOSFET has the same type of dopants in source/drain and channel while the doping level in the source/drain is much higher than that in the channel. Performance of DC, AC and variability of the uniformly doped, un-uniformly doped junctionless and conventional P-N junction MOSFETs featuring a gate length of 16 nm has been obtained by device simulation through Silvaco software package. Compared with uniformly doped junctionless MOSFETs, un-uniformly doped junctionless MOSFETs exhibit significantly improved overall DC and AC performance as well as lower sensitivity to variations of channel thickness. In addition, un-uniformly doped junctionless MOSFETs also demonstrate marginal performance enhancement compared with conventional P-N junction MOSFETs.

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A method to build reconfigurable architectures by extracting common subgraphs

A method to build reconfigurable architectures by extracting...

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2011 IEEE 9th International Conference on asic, asicON 2011

作者： Zhang, Tianyun Zhang, Rui Wang, Lingli Hu, Yu Software School Fudan University Shanghai 200433 China State Key Laboratory of ASIC and System Fudan University Shanghai 200433 China Electrical and Computer Engineering Department University of Alberta Canada

ISBN: (纸本)9781612841908

In this paper, we present a novel method to build reconfigurable architectures. Because an RTL description of a circuit can be converted to a data flow graph (DFG), our method is based on graph mining which aims to extract the common subgraphs among different benchmarks. A tool flow is proposed to convert benchmarks to data flow graphs and extract the common subgraphs. Benchmarks in the field of Error Checking and Correcting (ECC) are selected in the experiment to demonstrate that our method is correct and practical. © 2011 IEEE.

关键词： Data flow graphs

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Pattern transfer of nano-scale ferroelectric PZT gratings by a reversal nanoimprint lithography

Pattern transfer of nano-scale ferroelectric PZT gratings by...

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作者： Li, Zhi-Dong Shen, Zhen-Kui Hui, Wen-Yuan Qiu, Zhi-Jun Qu, Xin-Ping Chen, Yi-Fang Liu, Ran State Key Lab of Asic and System Department of Microelectronics Fudan University Shanghai 200433 China Rutherford Appleton Laboratory STFC Chilton Didcot Oxon OX11 0QX United Kingdom Micro and Nanotechnology Centre United Kingdom School of Microelectronics Fudan University 220 Handan Road Shanghai China

Nanoscale PZT gratings are successfully transferred to a Pt substrate using reversal nanoimprint technique without any chemical etch processes. The transfer process is preliminarily studied by measuring the surface topography of PZT coated on templates before transferring as well as the transferred patterns on substrates. Piezoelectric force microscopy (PFM) and Raman spectroscopy are used to investigate the transferred PZT nanostructures after annealing. Good ferroelectric and structural properties have been demonstrated by the transferred PZT nanostructures, indicating that this reversal imprint technique is applicable for forming nanoscale PZT domains, which may lead to the manufactures of high density data storage devices at economic cost. © 2011 Elsevier B.V. All rights reserved.

关键词： Nanoimprint lithography

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Switchable photonic crystals based on the photonic deformations of the azobenzene containing liquid crystal polymer

Switchable photonic crystals based on the photonic deformati...

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International Conference on Solid state Sensors and Actuators (TRANSDUCERS)

作者： Z. Yan Y.L. Yu X.M. Ji Department of Materials Science Fudan University Shanghai China State Key Laboratory of ASIC &System Department of Microelectronics Fudan University Shanghai China

A novel two-dimensional photonic crystal (PC) contained azobenzene crosslinked liquid-crystalline polymers (CLCPs) was fabricated by using the nanoimprinting technique. In accordance with the deformations induced by the photochemical reactions of these azobenzene CLCPs, on/off switch characteristics were observed by alternate irradiation with UV and visible light. A reflectance contrast of about 45% was realized under the excitation of 20 mW/cm 2 light intensity. And it exhibited a reversible switch behavior which indicated the high probability of the proliferation of numerous switching PC-based optical device applications.

关键词： Photonics Optical switches Crystals Optical polymers Optical films

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Low power discrete voltage assignment under clock skew scheduling 11

Low power discrete voltage assignment under clock skew sched...

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Asia and South Pacific Design Automation Conference

作者： Li Li Jian Sun Yinghai Lu Hai Zhou Xuan Zeng Electrical Engineering and Computer Science Department Northwestern University USA State Key Laboratory of ASIC & System Microelectronics Department Fudan University China

ISBN: (纸本)9781424475162

Multiple Supply Voltage (MSV) assignment has emerged as an appealing technique in low power IC design, due to its flexibility in balancing power and performance. However, clock skew scheduling, which has great impact on criticality of combinational paths in sequential circuit, has not been explored in the merit of MSV assignment. In this paper, we propose a discrete voltage assignment algorithm for sequential circuit under clock scheduling. The sequential MSV assignment problem is first formulated as a convex cost dual network flow problem, which can be optimally solved in polynomial time assuming delay of each gate can be chosen in continuous domain. Then a mincut-based heuristic is designed to convert the unfeasible continuous solution into feasible discrete solution while largely preserving the global optimality. Besides, we revisit the hardness of the general discrete voltage assignment problem and point out some misunderstandings on the approximability of this problem in previous related work. Benchmark test for our algorithm shows 9.2% reduction in power consumption on average, in compared with combinational MSV assignment. Referring to the continuous solution obtained from network flow as the lower bound, the gap between our solution and the lower bound is only 1.77%.

关键词： Delay Clocks Logic gates Power demand Sequential circuits Scheduling

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Investigation of ultra-thin Al2O3 film as Cu diffusion barrier on low-k (k=2.5) dielectrics

Investigation of ultra-thin Al2O3 film as Cu diffusion barri...

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IEEE International Conference on Interconnect Technology

作者： Shao-Feng Ding Qi Xie Fei Chen Hai-Sheng Lu Shao-Ren Deng Christophe Detavernier Guo-Ping Ru Yu-Long Jiang Xin-Ping Qu State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai China Department of Solid State Science Ghent University Ghent Belgium

Ultrathin Al 2 O 3 films were deposited by PEALD as Cu diffusion barrier on low-k (k=2.5) material. The thermal stability and electrical properties of the Cu/low k system with Al 2 O 3 layers with different thickness were studied after annealing. The AES, TEM and EDX results revealed that the ultrathin Al 2 O 3 films are thermally stable and have excellent Cu diffusion barrier performance. The electrical measurements of dielectric breakdown and TDDB tests further confirmed that the ultrathin Al 2 O 3 film is a potential Cu diffusion barrier in the Cu/low-k interconnects system.

关键词： Copper Aluminum oxide Films Annealing Silicon Dielectrics Thermal stability

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