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2023 IEEE 66th International Midwest Symposium on Circuits and systems, MWSCAS 2023

作者： Zhang, Jing Chen, Gengsheng Ke, Lingyun Ding, Luchang Fan, Xin Wu, Zehao Shen, Lei Cai, Chang Fudan University State Key Laboratory of Asic and System Shanghai China Shanghai Fudan Microelectronics Group Company Limited Shanghai China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9798350302103

Graph Neural Networks (GNNs) have achieved success in graph-based applications. Despite the proposed technologies are useful to speed up GNNs, the existing pruning methods still require extra costs and are hardly able to improve the hardware efficiency. Here, we propose a Block Variable-length Sampling Pruning (BVSP) method to balance the hardware workload, reduce the redundancy of graph structure, alleviate data sparsity, and improve the efficiency of hardware acceleration. Two sampling strategies for different scenarios are proposed. We evaluate our method on datasets and models, and it is verified that our method can achieve a pruning ratio of 10%to 50% and reduce the hardware scheduling workloads by 60% to 99% without any accuracy loss and extra costs. © 2023 IEEE.

关键词： Graph Neural Networks Graph Pruning Variable-length Workload

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Hydrodynamic constraints on the energy efficiency of droplet electricity generators

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Microsystems & Nanoengineering 2021年第3期7卷 209-218页

作者： Antoine Riaud Cui Wang Jia Zhou Wanghuai Xu Zuankai Wang State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai200433China Department of Mechanical Engineering City University of Hong KongHong Kong999077China

Electric energy generation from falling droplets has seen a hundred-fold rise in efficiency over the past few ***,even these newest devices can only extract a small portion of the droplet *** this paper,we theoretically investigate the contributions of hydrodynamic and electric losses in limiting the efficiency of droplet electricity generators(DEG).We restrict our analysis to cases where the droplet contacts the electrode at maximum spread,which was observed to maximize the DEG ***,the electro-mechanical energy conversion occurs during the recoil that immediately follows droplet *** then identify three limits on existing droplet electric generators:(i)the impingement velocity is limited in order to maintain the droplet integrity;(ii)much of droplet mechanical energy is squandered in overcoming viscous shear force with the substrate;(iii)insufficient electrical charge of the *** all these effects,we found that up to 83%of the total energy available was lost by viscous dissipation during *** this loss by using cascaded DEG devices to reduce the droplet kinetic energy may increase future devices efficiency beyond 10%.

关键词： viscous constraints limiting

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Advances in Noble Metal-Decorated Metal Oxide Nanomaterials for Chemiresistive Gas Sensors:Overview

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Nano-Micro Letters 2023年第6期15卷 353-427页

作者： Li‑Yuan Zhu Lang‑Xi Ou Li‑Wen Mao Xue‑Yan Wu Yi‑Ping Liu Hong‑Liang Lu State Key Laboratory of ASIC and System Shanghai Institute of Intelligent Electronics and SystemsSchool of MicroelectronicsFudan UniversityShanghai 200433People’s Republic of China School of Opto‑Electronic Information and Computer Engineering University of Shanghai for Science and TechnologyShanghai 200093People’s Republic of China State Key Laboratory of Metal Matrix Composites School of Material Science and EngineeringShanghai Jiao Tong UniversityShanghai 200240People’s Republic of China

Highly sensitive gas sensors with remarkably low detection limits are attractive for diverse practical application fields including real-time environmental monitoring,exhaled breath diagnosis,and food freshness *** various chemiresistive sensing materials,noble metal-decorated semiconducting metal oxides(SMOs)have currently aroused extensive attention by virtue of the unique electronic and catalytic properties of noble *** review highlights the research progress on the designs and applications of different noble metal-decorated SMOs with diverse nanostructures(e.g.,nanoparticles,nanowires,nanorods,nanosheets,nanoflowers,and microspheres)for high-performance gas sensors with higher response,faster response/recovery speed,lower operating temperature,and ultra-low detection *** key topics include Pt,Pd,Au,other noble metals(e.g.,Ag,Ru,and Rh.),and bimetals-decorated SMOs containing ZnO,SnO_(2),WO_(3),other SMOs(e.g.,In_(2)O_(3),Fe_(2)O_(3),and CuO),and heterostructured *** addition to conventional devices,the innovative applications like photo-assisted room temperature gas sensors and mechanically flexible smart wearable devices are also ***,the relevant mechanisms for the sensing performance improvement caused by noble metal decoration,including the electronic sensitization effect and the chemical sensitization effect,have also been summarized in ***,major challenges and future perspectives towards noble metal-decorated SMOs-based chemiresistive gas sensors are proposed.

关键词： Noble metal Bimetal Semiconducting metal oxide Chemiresistive gas sensor Electronic sensitization Chemical sensitization

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Electronics based on two-dimensional materials:Status and outlook

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Nano Research 2021年第6期14卷 1752-1767页

作者： Senfeng Zeng Zhaowu Tang Chunsen Liu Peng Zhou State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai200433China School of Computer Science Fudan UniversityShanghai200433China

Since Moore’s law in the traditional semiconductor industry is facing shocks,More Moore and More than Moore are proposed as two paths to maintain the development of the semiconductor industry by adopting new architectures or new materials,in which the former is committed to the continued scaling of transistors for performance enhancement,and the latter pursues the realization of functional diversification of electronic ***-dimensional(2D)materials are supposed to play an important role in these two *** More Moore,the ultimate thin thickness and the dangling-bond-free surface of 2D channels offer excellent gate electrostatics while avoiding the degradation of carrier mobility at the same time,so that the transistors can be further scaled down for higher *** More than Moore,devices based on 2D materials can well meet the requirements of electronic systems for functional diversity,like that they can operate at high frequency,exhibit excellent sensitivity to the changes in the surroundings at room temperature,have good mechanical flexibility,and so *** this review,we present the application of 2D materials in More Moore and More than Moore domains of electronics,outlining their potential as a technological option for logic electronics,memory electronics,radio-frequency electronics,sensing electronics,and flexible electronics.

关键词： More Moore More Than Moore two-dimensional materials transition metal dichalcogenides(TMDs)

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A CFET Unit Cell based MUX21 design strategy 16

A CFET Unit Cell based MUX21 design strategy

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Zhu, Xiao-Na Wei, Chen-Cheng Ding, Rong-Zheng Yu, Shao-Feng Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai200433 China Jiashan Fudan Institute China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

With the Moore's law approaching ultimate limitation, device structure has been revolutionary changing, from FinFET to GAA FET, and then a new semiconductor device structure, CFET, has been regarded the continuing structure after GAA. CFET has significant area miniaturization advantages, but its folding N/PFET vertically brings new difficulties in process flow and new strategies for design enablement like in standard cell library. In this paper, we proposed the design consideration priority in CFET unit cell constructed standard cell library, and give examples like MUX21in obeying our rule. Two different schematics of MUX21 are designed at multiple levels: process flow, layout, and circuit performance. The proposed rule in CFET unit cell for standard library cell and the specific DTCO flow in this MUX21 circuit can provide the pathway for other circuit designs of standard cell library composed of CFET unit cell. © 2022 IEEE.

关键词： Cytology

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High-Dimensional Analog Circuit Sizing via Bayesian Optimization in the Variational Autoencoder Enhanced Latent Space

High-Dimensional Analog Circuit Sizing via Bayesian Optimiza...

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Electronics Design Automation (ISEDA), International Symposium of

作者： Wangzhen Li Zhaori Bi Xuan Zeng Microelectronics Department State Key Lab of ASIC & System Fudan University Shanghai China

ISBN: (数字)9798350352030

ISBN: (纸本)9798350352047

High-dimensional analog circuit sizing with machine learning-based surrogate models suffers from the high sampling cost of evaluating expensive black-box objective functions in huge design spaces. This work addresses the sampling efficiency challenge by elaborately reducing the dimensionality of the input spaces, enabling efficient optimization for automated analog circuit sizing. We propose a latent space optimization method that includes an iteratively updated generative model based on a variational autoencoder to embed the solution manifold of analog circuits to a low-dimensional and continuous space, where the latent variables are optimized using Bayesian optimization. The effectiveness of the proposed method has been verified on two real-world analog circuits with 18 and 59 design variables. In comparison with BO in the original high-d spaces or latent low-d spaces assisted by other embedding strategies, the proposed method achieves 23%~73% improvements in optimization per-formance within the same runtime limitations. We also conduct a technology migration experiment using the pre-trained variational autoencoder model, which demonstrates the necessity of pre-training and the scalability of the proposed method.

关键词： Manifolds Runtime Design automation Costs Scalability Optimization methods Closed box

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A 400-MS/s 12-bit Voltage-Time Hybrid ADC with a Ping-Pong SAR TDC for Speed Enhancement

A 400-MS/s 12-bit Voltage-Time Hybrid ADC with a Ping-Pong S...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Yutong Zhao Yuguo Xiang Fan Ye Junyan Ren Department of Microelectronics State Key Laboratory of ASIC and System Fudan University Shanghai China

This paper presents a 400-MS/s 12-bit voltage-time hybrid pipeline ADC in a 28 nm CMOS process. The first stage is an asynchronous SAR ADC resolving 6 bits, and the second stage is a time-domain ADC composed of a VTC and a 7-bit SAR TDC (with 1-bit redundancy). To speed up the time domain operation, a ping-pong switching technique is used in the second stage. Besides, a common mode VTC is adopted to improve the linearity during the voltage-to-time conversion. A non-binary SAR TDC is also designed to tolerate the MSBs decision errors in the time-domain quantization. Furthermore, a LMS-based background calibration is performed to correct the capacitor mismatch error, interstage gain error, and bit-weight in the SAR TDC. The simulation results show that this design achieves a SNDR of 63.3 dB and a SFDR of 79.1 dB at Nyquist input. The power consumption is 9.6 mW with a supply of 0.9V, showing a FoM of 20.1 fJ/conversion-step.

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SS-DGD: Scalable Short-Entry Dual-Grain Coherence Directoris 16

SS-DGD: Scalable Short-Entry Dual-Grain Coherence Directoris

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Tang, Yuxin Qiu, Yudi Liu, Yanwei Jiao, Jie Zhang, Peng Fan, Yibo Fudan University State Key Laboratory of Asic and System Department of Microelectronics Shanghai China Peking University Advanced Institute of Information Technology Beijing China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

As the number of cores in a chip multiprocessor increase, the directory area overhead becomes excessive. Current research shows that directory area can be reduced by tracking private entries with coarse-grain region entries. The insight is that contiguous memory blocks are often accessed by a single core. In order to indicate which blocks the region owner has cached, a bit vector format is applied in the dual-grain directory (DGD). However, this limits scalability and is incompatible with the latest scalable directories. In this paper, we propose a scalable short-entry dual-grain coherence directory (SS-DGD). In private region entries, a counter is used instead of the original bit vector. To reduce the directory area, we use a separate short-entry directory to store private block entries with a pointer format and region entries with counters. The detailed simulation-based study in 64-core CMPs shows that our proposal can reduce the area overhead by 29.9% compared with DGD. © 2022 IEEE.

关键词： Computer architecture

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Automated Design of Complex Analog Circuits with Multiagent Based Reinforcement Learning 23

Automated Design of Complex Analog Circuits with Multiagent ...

引用

Proceedings of the 60th Annual ACM/IEEE Design Automation Conference

作者： Jinxin Zhang Jiarui Bao Zhangcheng Huang Xuan Zeng Ye Lu State Key Lab. of ASIC & System School of Information Science and Technology Frontier Institute of Chip and System State Key Lab. of ASIC & System Microelectronics Department Fudan University Shanghai China

ISBN: (纸本)9798350323481

Despite the effort of analog circuit design automation, currently complex analog circuit design still requires extensive manual iterations, making it labor intensive and time-consuming. Recently, reinforcement learning (RL) algorithms have been demonstrated successfully for the analog circuit design optimization. However, a robust and highly efficient RL method to design analog circuits with complex design space has not been fully explored yet. In this work, inspired by multiagent planning theory as well as human expert design practice, we propose a multiagent based RL (MA-RL) framework to tackle this issue. Particularly, we (i) partition the complex analog circuits into several sub-blocks based on topology information and effectively reduce the complexity of design search space; (ii) leverage MA-RL for the circuit optimization, where each agent corresponds to a single sub-block, and the interactions between agents delicately mimic the best design tradeoffs between circuit sub-blocks by human experts; (iii) introduce the multiagent twin-delayed techniques to further boost training stability and accomplish higher performances. Experiments on two different analog circuit topologies and knowledge transfers between two technology nodes are demonstrated. It's shown that MA-RL framework can achieve the best FoM for complex analog circuits design. This work shines the light for future large scale analog circuit system design automation.

关键词： complex analog circuits

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A 12.87-dB Gain 10.5-dBm OPldB60-to-66-GHz LNA in 0.15-μm GaAs pHEMT Technology

A 12.87-dB Gain 10.5-dBm OPldB60-to-66-GHz LNA in 0.15-μm G...

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2022 IEEE the Asia Pacific Conference on Postgraduate Research in microelectronics and Electronics, PrimeAsia 2022

作者： Li, Xuefeng Wang, Yuting Wu, Tianxiang Chen, Yong Ren, Junyan Ma, Shunli School of Microelectronics Fudan University State Key Laboratory of ASIC and System Shanghai China State Key Laboratory of ASIC and System School of Information Science and Technology Fudan University Shanghai China University of Macau State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST Macao China

ISBN: (纸本)9781665450690

This paper presents a V-band low noise amplifier (LNA) implemented in a 0.15-μm Gallium Arsenide (GaAs) pseudomorphic high electron-mobility transistor (pHEMT) technology. The LNA adopts a three-stage common-source (CS) topology. Each transistor has a bias circuit, and the microstrip-line inductor is used to realize the input noise matching network, the interstage, and the output matching network. Circuit simulations show that our LNA scores a 12.87-dB small-signal gain, the 3-dB bandwidth ranges from 60 GHz to 66 GHz, and the current consumption is 30 mA under a 5-V supply voltage. Its noise figure is 5.9 dB, and the output 1-dB compression point is 10.5 dBm. The chip area is 1.32× 1.5mm2. © 2022 IEEE.

关键词： Low noise amplifiers

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