The electrical levels of defects of high- k dielectric Zr O2 films deposited with different oxygen fluxes have been investigated using x-ray diffraction, x-ray photoelectron spectroscopy, and spectroscopic ellipsometr...
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We report the chemical self-assembly growth of Au nanocrystals on atomic-layer-deposited HfO2 films aminosilanized by (3-Aminopropyl)-trimethoxysilane aforehand for memory applications. The resulting Au nanocrystals...
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We report the chemical self-assembly growth of Au nanocrystals on atomic-layer-deposited HfO2 films aminosilanized by (3-Aminopropyl)-trimethoxysilane aforehand for memory applications. The resulting Au nanocrystals show a density of about 4 × 10^11 cm^-2 and a diameter range of 5-8nm. The metal-oxide-silicon capacitor with double-layer Au nanocrystals embedded in HfO2 dielectric exhibits a large C - V hysteresis window of 11.9 V for ±11 V gate voltage sweeps at 1MHz, a flat-band voltage shift of 1.5 V after the electrical stress under 7 V for 1ms, a leakage current density of 2.9 × 10^-8 A/cm^-2 at 9 V and room temperature. Compared to single-layer Au nanocrystals, the double-layer Au nanocrystals increase the hysteresis window significantly, and the underlying mechanism is thus discussed.
Multilayers of poly(p-xylyleneviologen) (PXV) and calf thymus DNA were constructed on the gold surface by layer-by-layer (LBL) method. The assembly process was examined by quartz crystal microbalance (QCM) measurement...
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This paper presents a novel phase discriminator called robust digital phase discriminator (RDPD) for the one-bit analog-to-digital conversion (ADC) software-defined receivers. Different from existing digital phase dis...
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In this work, a trilayer technique used in the nanoimprint lithography process to replicate the templates is developed. The SU-8/SiO 2/PMMA trilayer was used. The photosensitive epoxy (SU8 resist) which has a low glas...
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Since low-density parity-check codes have near-capacity decoding performance and very high decoding throughput, they have been employed as FEC coding scheme in many transmission standards for wireless communication, s...
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Since low-density parity-check codes have near-capacity decoding performance and very high decoding throughput, they have been employed as FEC coding scheme in many transmission standards for wireless communication, such as IEEE 802.22n, IEEE 802.16e, DVB-S2, and DTMB. This trend triggers the need for so-called multi-standard LDPC decoders. In this paper, a flexible architecture that supports multiple code rates, variable block sizes and is code independent for block-LDPC codes is proposed, based on rearranged TPMP algorithm,. By implementing a dynamically reconfigurable RPPU, our proposed architecture can be configured into row update or column update mode by time-division multiplexing. Consequently, the decoder achieves a high area and power efficiency. To verify our proposed architecture, a novel LDPC decoder which supports IEEE802.16e standard has been implemented. The results on a 0.18 um CMOS process show that the decoder occupies an area of approximately 13.7 mm 2 and runs correctly at an maximum operating frequency of 110 MHz, resulting in 98 Mbps decoding throughput.
Data retention characteristics and a failure mechanism of TaN/Cu xO/Cu resistive memory device are investigated by a temperature-accelerated test method. Data retention capability at 85 °C is sufficiently longer ...
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Based on the min-sum algorithm, this paper proposes an LDPC decoder integrating the TDMP schedule, which could achieve low complexity as well as good performance. The LDPC decoder is for DVB-S2, which includes 11 kind...
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Based on the min-sum algorithm, this paper proposes an LDPC decoder integrating the TDMP schedule, which could achieve low complexity as well as good performance. The LDPC decoder is for DVB-S2, which includes 11 kinds of code rates with a block size of 64800. Based on SMIC 0.13 ¿m standard CMOS process, the LDPC decoder has an estimation area of 14 mm 2 , a throughput of 135 Mbps with a frequency of 105 MHz and maximum iteration number of 30,which shows advantage over previous DVB-S2 LDPC decoders.
This paper presents a 4096-point FFT processor for CMMB receiver system, in which dual-path pipelined shared memory architecture is employed. With a data reordering for receiver, an elaborate memory configuration sche...
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This paper presents a 4096-point FFT processor for CMMB receiver system, in which dual-path pipelined shared memory architecture is employed. With a data reordering for receiver, an elaborate memory configuration scheme, single-port SRAM can be adopted without degrading throughput rate, with small area and lower power dissipation. In addition, the Signal-to-Quantization Noise Ratio (SQNR) of a 4 K-point fixed-point FFT can achieve 48.7 B with the wordlength of 12 bit.
In the lately released Chinese mobile multimedia broadcasting standard CMMB, cyclic-prefix based OFDM technique has been adopted. Traditional timing synchronization for this system requires a correlator to correlate t...
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In the lately released Chinese mobile multimedia broadcasting standard CMMB, cyclic-prefix based OFDM technique has been adopted. Traditional timing synchronization for this system requires a correlator to correlate the last Ng samples of the received OFDM symbol with their copies ahead, and at least N (the length of OFDM symbol) data and Ng correlation results have to be stored for implementation, which results in large consumption of memory. In this paper, a low complexity scheme for the joint synchronization of symbol timing and fractional carrier frequency is proposed. This scheme extremely lowers the hardware cost, especially the memory consumption. Simulation results show that the performance of this algorithm can also meet the need of the system well over both AWGN and typical CMMB multipath channel.
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