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Algorithm based on mixed boundary element integral formulations for extracting frequency-dependent impedances of 3D VLSI interconnects

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics 2007年第10期19卷 1252-1258页

作者： Gong, Fang Yu, Wenjian Yan, Changhao Wang, Zeyi Department of Computer Science and Technology Tsinghua University Beijing 100084 China State Key Laboratory of ASIC and System Fudan University Shanghai 201203 China

Based on the mixed boundary element method, this paper proposes several techniques for 3D impedance extraction, including an efficient organization and row-column adjustment of the sparse coefficient matrix, and a pre-conditioned iterative equation solver. A fast impedance extractor is formed with these techniques. The proposed method has faster speed than the newly-developed FastImp by MIT, while preserving high accuracy. Numerical experiments on two typical interconnect structures verify the efficiency of this method.

关键词： Boundary element method FastImp Generalized minimal residual (GMRES) Impedance extraction Mixed boundary element method Pre-condition

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Digital Correlation Demodulator Design for RFID Reader Receiver

Digital Correlation Demodulator Design for RFID Reader Recei...

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IEEE Conference on Wireless Communications and Networking

作者： Yuan Liu Chenling Huang Hao Min Guohong Li Yifeng Han Department of Microelectronics State Key Laboratory of ASIC & System Fudan University Shanghai China Mercury Technology (Shanghai) Company Limited Shanghai China

A high performance digital demodulator for RFID reader receiver is proposed. After carefully analyzing the characteristics of the received data, correlation operation is introduced into the demodulator to estimate the frequency of the received data and decode them. Simulation result indicates that this demodulator can work well under the 6dB input signal-to-noise ratio (SNR) with +/- 22% frequency deviation tolerance. FPGA implementation result shows that the communication distance between reader and tag can be extended to 5m above by the use of this demodulator.

关键词： Demodulation Radiofrequency identification Frequency estimation Field programmable gate arrays Decoding Frequency synchronization Signal processing Radio frequency Communications Society microelectronics

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A Novel reconfigurable VLSI architecture for motion estimation

A Novel reconfigurable VLSI architecture for motion estimati...

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International Conference on asic

作者： Cao Wei Hou Hui Lai Jin Mei Mao Zhi Gang Tong Jia Rong Min Hao State Key Laboratory of ASIC and System Fudan University Shanghai China Microelectronics Center Harbin Institute of Technology Harbin China

A new reconfigurable multi-BMA VLSI architecture was proposed to select different levels of trade-off between video quality, computing complexity and power for power aware applications. The architecture can reuse the smaller blocks' SADs to calculate 41 motion vectors of a 16times16 block in parallel for H.264's VBSME. TSMC 0.18 um CMOS technology was adopted and the circuit's power consumption can be changed between 13.8 and 247 mW with the typical algorithms. Under a clock frequency of 157 Mhz, the architecture allows the real-time processing of VGA at 30 fps with FS in a search range [-16, +15] at the high level.

关键词： Very large scale integration Motion estimation Computer architecture Energy consumption Image quality CMOS technology Circuits Clocks Frequency Switches

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Traffic Splitting with Network Calculus for Mesh Sensor Networks

Traffic Splitting with Network Calculus for Mesh Sensor Netw...

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International Conference on Future Generation Communication and Networking (FGCN)

作者： Huimin She Zhonghai Lu Axel Jantsch Li-Rong Zheng Dian Zhou ASIC & System State Key Laboratory Department of Microelectronics Fudan university Shanghai China Department of Electronic Computer and Software Systems Royal Institute of Technology Sweden

In many applications of sensor networks, it is essential to ensure that messages are transmitted to their destinations as early as possible and the buffer size of each sensor node is as small as possible. In this paper, we firstly propose a mesh sensor network system model. Based on this system model, the expressions for deriving the delay bound and buffer requirement bound are presented using network calculus. In order to balance traffic load and improve resource utilization, three traffic splitting mechanisms are proposed. The numerical results show that the delay bound and buffer requirement bound are lowered while applying those traffic splitting mechanisms. And thus the performance of the whole sensor network is improved.

关键词： Telecommunication traffic Calculus Traffic control Sensor systems Delay Wireless sensor networks Network topology Routing Packet switching Computer networks

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Heuristic complete algorithm for SAT problem by approximation solution

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics 2007年第9期19卷 1184-1189页

作者： Jing, Ming'e Zhou, Dian Tang, Pushan Zhou, Xiaofang ASIC and System State Key Laboratory Fudan University Shanghai 201203 China Electronic Engineering Department University of Texas at Dallas TX 75083 United States

The advantages of complete algorithm and incomplete algorithm of the SAT problem are integrated into an algorithm. First, an approximation solution is obtained by an incomplete algorithm, as an initial input of the complete algorithm, which is used to phase decision of branched variable. The algorithm guides the complete algorithm first search the subspace that the approximation solutions lie in, which accelerates the process that the solver find the satisfied solution and provides a new approach for SAT problem. Experimental results show that proposed algorithm improves the decision precision and the efficiency of solver and performs well in many instances.

关键词： Complete algorithm Decision making Local search SAT problems

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An efficient transformation method for DFRM expansions

An efficient transformation method for DFRM expansions

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International Conference on asic

作者： H. Xu M. Yang L. Wang J.R. Tong A.E.A. Almaini Tianjin Vocational College of Mechanics and Electricity Tianjin China State Key Laboratory of ASIC & System Microelectronics Department Fudan University Shanghai China School of Engineering Napier University Edinburgh UK

Dual Form of Reed-Muller (DFRM) expansions with fixed polarity are derived from Reed-Muller (RM) expansions by using the operation of Kronecker matrix products. An efficient decomposition method is proposed based on the formulation. The method can be used for the transformation between from DFRM expansions to RM expansions within the same fixed polarity as well. Hence, the proposed method is bidirectional. After decomposition, the calculation of the duplicated matrix is avoided, resulting in less computation time. Time complexity of the algorithm is 0(2 1.5n ). The time used for small variables is virtual zero for the tested MCNC benchmarks. For large variable, it still works very well and achieves less than 20 seconds for 25-variable benchmark. In the implementation, only on-set coefficients are used. Consequently, the space complexity is O(M), where M is the number of on-set coefficients. It makes simultaneous optimization in both RM and DFRM expansions possible.

关键词： Circuit synthesis Circuit testing Logic testing Matrix decomposition Benchmark testing Electronic design automation and methodology Arithmetic Algebra Logic design Logic circuits

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Fast On-Line Task Placement and Scheduling on Reconfigurable Devices

Fast On-Line Task Placement and Scheduling on Reconfigurable...

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International Conference on Field Programmable Logic and Applications

作者： XueGong Zhou Ying Wang XunZhang Huang ChengLian Peng ASIC & System State-Key Laboratory Fudan University Shanghai China Department of Computing and Information Technology Fudan University Shanghai China

This paper focus on on-line placement and scheduling of tasks with known executing time on reconfigurable devices. The notion of recognition-earliest for scheduling algorithms is introduced, that is the algorithm can arrange the start time of a newly arrived task as early as possible. A new scheduling algorithm is proposed. By exploit the knowledge about temporal properties of each task, the algorithm attains recognition-earliest. A fast placement algorithm is also presented. The evaluation results show that the proposed placement algorithm is one of the fastest algorithm, and the proposed scheduling algorithm achieves the best performance compared with previous algorithms, while has a quite low runtime cost.

关键词： Scheduling algorithm Processor scheduling Hardware Field programmable gate arrays Runtime Costs Operating systems Application specific integrated circuits Information technology Delay

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A Sparse Grid based Spectral Stochastic Collocation Method for Variations-Aware Capacitance Extraction of Interconnects under Nanometer Process Technology

A Sparse Grid based Spectral Stochastic Collocation Method f...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Hengliang Zhu Xuan Zeng Wei Cai Jintao Xue Dian Zhou ASIC & System State Key Lab Microelectronics Department Fudan University Shanghai China Department of Mathematics North Carolina State University Charlotte USA E.E. Department University of Texas Dallas USA

ISBN: (纸本)9783981080124

In this paper, a spectral stochastic collocation method (SSCM) is proposed for the capacitance extraction of interconnects with stochastic geometric variations for nanometer process technology. The proposed SSCM has several advantages over the existing methods. Firstly, compared with the PFA (principal factor analysis) modeling of geometric variations, the K-L (Karhunen-Loeve) expansion involved in SSCM can be independent of the discretization of conductors, thus significantly reduces the computation cost. Secondly, compared with the perturbation method, the stochastic spectral method based on homogeneous chaos expansion has optimal (exponential) convergence rate, which makes SSCM applicable to most geometric variation cases. Furthermore, sparse grid combined with a MST (minimum spanning tree) representation is proposed to reduce the number of sampling points and the computation time for capacitance extraction at each sampling point. Numerical experiments have demonstrated that SSCM can achieve higher accuracy and faster convergence rate compared with the perturbation method

关键词： Stochastic processes Capacitance Perturbation methods Sampling methods Solid modeling Conductors Computational efficiency Chaos Convergence Grid computing

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RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect

RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Prese...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Fan Yang Xuan Zeng Yangfeng Su Dian Zhou ASIC & System State Key Lab Microelectronics Department Fudan University Shanghai China Mathematics Department Fudan University Shanghai China E.E. Department University of Texas Dallas Richardson TX USA

This paper aims to explore RLC equivalent circuit synthesis method for reduced-order models of interconnect circuits obtained by Krylov subspace based model order reduction (MOR) methods. To guarantee pure RLC equivalent circuits can be synthesized for the reduced-order models, both the structures of input and output incidence matrices and the block structure of the circuit matrices should be preserved in the reduced-order models. Block structure preserving MOR methods such as SPRIM (Freund, 2004) and SAPOR (Su et al., 2004) have been well established. In this paper, an embeddable input-output structure preserving order reduction (IOPOR) technique was proposed to further preserve the structures of input and output incidence matrices in the reduced-order models. By combining block structure preserving MOR methods and IOPOR technique, an RLC equivalent circuit synthesis method RLCSYN (RLC SYNthesis) was developed. Inline diagonalization and regularization techniques are specifically proposed to enhance the robustness of inductance synthesis. The pure RLC model, high modeling accuracy, passivity guaranteed property and SPICE simulation robustness make RLCSYN more applicable in interconnect analysis, either for digital IC design or mixed signal IC simulation.

关键词： Equivalent circuits Circuit synthesis Reduced order systems Integrated circuit interconnections Integrated circuit modeling Signal synthesis RLC circuits Robustness Analytical models Digital integrated circuits

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Nano-crystalline phase change memory with composite Si-Sb-Te film for better data retention and lower operation current

Nano-crystalline phase change memory with composite Si-Sb-Te...

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IEEE International Memory Workshop (IMW)

作者： Y. Y. Lin H. B. Lv P. Zhou M. Yin F. F. Liao Y. F. Cai T. A. Tang J. Feng Y. Zhang Z. F. Zhang B. W. Qiao Y. F. Lai B. C. Cai B. Chen Department of Microelectronics ASIC&System State Key Lab Fudan University Shanghai China Research Institute of Micro/Nanometer Technology Shanghai Jiaotong University Shanghai China Silicon Storage Technology Inc. Sunnyvale CA USA

Si-Sb-Te (SST) system materials were investigated for non-volatile phase change memory application. By contrast to the conventional GST films, the SST films exhibit stronger thermal stability and smaller RESET current, which were resulted from the self-confine and self-heat mechanisms by the amorphous Si-rich regions surrounding the phase change crystalline in SST. It shows a good promise for non-volatile memory applications.

关键词： Phase change memory Semiconductor films Conductivity Phase change materials Nonvolatile memory Thermal stability Crystallization Thermal resistance Thermal stresses Temperature

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