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ICSICT-2006: 2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Sun, Shilei Xue, Jintao Liu, Li Wang, Gaofeng Computer School Wuhan University Wuhan 430072 China State Key Laboratory of ASIC and System Fudan University Shanghai 200433 China Institute of Microelectronics and Information Technology Wuhan University Wuhan 430072 China

ISBN: (纸本)1424401615

A fast interconnect capacitance extraction engine is realized and presented here. Employing a fast multipole accelerated Generalized Minimal Residual (GMRES) based three-dimensional (3-D) field solver, this software tool can quickly and accurately extract parasitic capacitances of arbitrary interconnects embedded in piece-wise constant dielectrics. This engine is also capable of performing fast and accurate capacitance extraction for critical nets in Radio Frequency (RF) applications, IC designs, and MicroElectroMechanical systems (MEMS). The architecture of this extraction engine is described. Numerical examples are included to validate the extraction engine and demonstrate the capabilities of this extraction engine. © 2006 IEEE.

关键词： Capacitance

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Investigation of Ru/TaN on low dielectric constant material with k=2.7

Investigation of Ru/TaN on low dielectric constant material ...

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2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Jing-Jing Tan Qi Xie Mi Zhou Tao Chen Yu-Long Jiang Xin-Ping Qu ASIC & System State Key Lab. Department of MicroelectronicsFudan University

ISBN: (纸本)1424401607

The properties of the Ruthenium(Ru)/TaN as copper diffusion barrier in copper low dielectric constant material(low-k) metallization were studied by sheet resistance,X-ray diffraction(XRD),X-ray photoelectron spectroscopy(XPS),transmission electron microscopy(TEM) and electrical Current leakage-Voltage ***,Ru and TaN thin films were deposited by ion beam sputtering *** resistance and XRD results demonstrate that there was little inter-diffusion with ascending annealing *** XPS spectra indicate that Ru was partially oxidized and no inter reaction with low-k was *** images show that copper appeared into barriers when the sample was annealed at 400℃/30min, and it is revealed that copper diffused into low-k at 500℃/30min from theⅠ-Ⅴtest.

关键词： Investigation of Ru/TaN on low dielectric constant material with k

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Investigation of Ni reaction with amorphous SiGeC thin film

Investigation of Ni reaction with amorphous SiGeC thin film

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2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Tao Chen Jian-Ping Liu Mi Zhou Wei Wang Jing-Jing Tan Xin-Ping Qu ASIC&System State Key Lab. Department of MicroelectronicsFudan University

ISBN: (纸本)1424401607

The reaction between Ni and amorphous SiGeC thin film on SiO substrate is *** point probe（FPP）,X-ray diffraction（XRD） and Auger electron spectroscopy（AES） depth profiling are used to check the sheet resistance,the phase formation and atomic distribution during the *** is found that comparing with Ni reaction withα-SiGe,thephase change of Ni reaction withα-SiGeC is *** 700℃annealing a tetragonal phase ofη-NiSi is formed during the Ni reaction withα-*** atoms diffuse to the surface at a higher temperature and cause the lattice constant decrease of the formed Ni（SiGe） film.

关键词： XRD Investigation of Ni reaction with amorphous SiGeC thin film

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A capacitive step-down converter using a linear mode pre-regulator for improved load regulation

A capacitive step-down converter using a linear mode pre-reg...

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ICSICT-2006: 2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Shao, Bin Yang, Yujia Hong, Zhiliang Xu, Chihao Killat, Dirk State Key-Laboratory of ASIC and Systems Fudan University Shanghai 201203 China Department of Microelectronics Saarland University Saarbruecken 66123 Germany Dialog Semiconductor Kirchheim-Teck 73230 Germany

ISBN: (纸本)1424401615

A capacitive step-down converter in 0.25 μm CMOS using a linear mode pre-regulator is presented. The linear pre-regulator operates both in pulse frequency mode under low load conditions and in current mode under high output load. In pulse frequency mode the pre-regulator limits the charge current of the capacitor network improving the electromagnetic compatibility. Under high load conditions the converter operates in a current mode which means that the switched capacitors are clocked with a fixed duty cycle ratio and the regulation of the output voltage is performed by the pre-regulator. ©2006 IEEE.

关键词： Electric converters

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Implementation of a CMOS down-conversion mixer for GSM1900 receivers

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

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Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors 2006年第3期27卷 467-472页

作者： Chu, Fangqing Li, Wei Su, Yanfeng Ren, Junyan State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai 201203 China Shanghai Sicomm RF Technology Incorporation Shanghai 200433 China

A 1.9 GHz down-conversion CMOS mixer with a novel folded Gilbert cell, intended for use in GSM1900 (PCS1900) low-IF receivers, is fabricated in a RF 0.18 μm CMOS process. The prototype demonstrates good performance at an intermediate frequency of 100 kHz. It achieves a conversion gain of 6 dB, SSB noise figure of 18.5 dB (1 MHz IF), and IIP3 11.5 dBm while consuming a 7 mA current from a 3.3 V power supply.

关键词： Mobile telecommunication systems

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Fast Conversion for Large Canonical OR-Coincidence Functions

Fast Conversion for Large Canonical OR-Coincidence Functions

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IEEE Asia-Pacific Conference on Circuits and systems

作者： M. Yang L. Wang A.E.A. Almaini State Key Laboratory of ASIC & System Microelectronics Department Fudan University Shanghai China School of Engineering Napier University Edinburgh UK

Fixed polarity canonical OR-coincidence (COC) expansions based on inclusive-OR and OR operations are dual forms of fixed polarity Reed-Muller expansions. Traditionally, they are obtained from maxterms of canonical products-of-sum (CPOS) expansions. Two conversion methods are proposed for generating fixed polarity COC expansions. The first proposed method called maxterm method is based on traditional maxterm method. Fast conversion speed is achieved after the coefficients were divided into several segments to reduce the duplication of the calculation. The second proposed method called minterm method generates fixed polarity COC expansions directly from programmable logic array (PLA) files. The minterm method can on average achieve 37.57% speed improvement over the maxterm method. Both algorithms outperform published work significantly

关键词： Programmable logic arrays Logic functions Circuit synthesis Circuit testing Central Processing Unit Laboratories Application specific integrated circuits microelectronics Signal processing algorithms Digital circuits

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A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations

A Spectral Stochastic Collocation Method for Capacitance Ext...

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IEEE Asia-Pacific Conference on Circuits and systems

作者： Hengliang Zhu Xuan Zeng Wei Cai Dian Zhou ASIC & System State Key Laboratory Microelectronics Department Fudan University Shanghai China Department of Mathematics University of North Carolina Charlotte USA

In this paper, a spectral stochastic collocation method (SSCM), is proposed for the capacitance extraction of interconnects with either on-chip process variations or off-chip rough surfaces. The proposed method is based on the stochastic spectral method combined with sparse grid technique, and has several advantages over the existing methods. Compared with the perturbation method, the stochastic spectral method based on homogeneous chaos expansion has exponential convergence rate, which makes it very promising for parasitic extraction with process variations. Furthermore, the sparse grid technique significantly reduces the amount of sampling points compared with Monte Carlo method, and greatly saves the computation time for capacitance extraction. Numerical experiments have demonstrated that SSCM can achieve higher accuracy while having the same efficiency compared with the existing methods

关键词： Stochastic processes Capacitance Chaos Integrated circuit interconnections Rough surfaces Surface roughness Perturbation methods Surface topography Conductors Solid modeling

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A Capacitive Step-Down Converter Using a Linear Mode Pre-Regulator for Improved Load Regulation

A Capacitive Step-Down Converter Using a Linear Mode Pre-Reg...

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2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Shao Bin Yang Yujia Hong Zhiliang Xu Chihao Dirk Killat State Key-Laboratory of ASIC ＆ Systems Fudan University Department of Microelectronics Saarland University

ISBN: (纸本)1424401607

A capacitive step-down converter in 0.25μm CMOS using a linear mode pre-regulator is *** linear pre-regulator operates both in pulse frequency mode under low load conditions and in current mode under high output *** pulse frequency mode the pre-regulator limits the charge current of the capacitor network improving the electromagnetic compatibility. Under high load conditions the converter operates in a current mode which means that the switched capacitors are clocked with a fixed duty cycle ratio and the regulation of the output voltage is performed by the pre-regulator.

关键词： PFM A Capacitive Step-Down Converter Using a Linear Mode Pre-Regulator for Improved Load Regulation

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A Novel On-chip Debug system with Quick All-registers Scan Chain Based on JTAG

A Novel On-chip Debug System with Quick All-registers Scan C...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Yang Liu Wang-hua Wu Xiao-fang Zhou Dian Zhou Department of Microelectronics ASIC & Systems State Key Laboratory Fudan University Shanghai China

ISBN: (纸本)1424401607

JTAG defines a serial interface to access test-dedicated logic embedded in integrated circuits. As an extension, a test platform based on JTAG standard can support general verifications and debug functions for SOC. The paper presents an on-chip debug system based on JTAG standard for embedded microprocessors. It provides powerful functions for the system. For example, hardware breakpoints, single step execution mode, monitoring the registers, programming. An all-registers structure is used to support quick all-registers monitoring functions. Moreover, the paper contributes to the research of no-gap transfer of debug functions

关键词： system-on-a-chip Circuit testing Registers Control systems Integrated circuit testing Hardware microelectronics Logic testing Monitoring Computer architecture

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Modified Reynolds equation for squeeze-film air damping of slotted plates in MEMS devices

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

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Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors 2006年第3期27卷 473-477页

作者： Sun, Yuancheng Bao, Minhang Yang, Heng Huang, Yiping State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai 200433 China State Key Laboratory of Transducer Technologies Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Shanghai 200050 China

A differential equation for calculating squeeze-film air damping in slotted plates is developed by modifying the Reynolds equation. A term is added to account for the effect of airflow through the slots on the air damping of the plate. The end effect of the airflow in the slots is also treated by substituting an effective channel length for the geometric channel length (i.e. the thickness of the plate). The damping pressure distribution, damping force, and damping force coefficient of the slotted plates can be found by solving the equation under appropriate boundary conditions. With restrictions on the thickness and the lateral dimensions of the slotted plate removed, the equation provides a useful tool for analysing the squeeze-film air damping effect of slotted plates with finite thickness and finite lateral dimensions. For a typical slotted plate structure, the damping force coefficient obtained by this equation agrees well with that generated by ANSYS.

关键词： Microelectromechanical devices

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