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作者： Li, Zhen Zheng, Su Zhang, Jide Lu, Yao Gao, Jingbo Tao, Jun Wang, Lingli Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai201203 China

Approximate computing is an efficient approach to reduce the design complexity for error-resilient applications. Multipliers are key arithmetic units in many applications, such as deep neural networks (DNNs) and digital signal processing (DSP) systems. In this article, an open-source adaptable approximate multiplier design driven by input distribution and polarity is proposed to generate optimized approximate multipliers to trade off between the application-level performance and the hardware cost. The proposed method minimizes the average square of the absolute error of an approximate multiplier according to the probability distributions of operands extracted from the target application with consideration of input polarity, achieving low hardware cost and negligible application-level performance loss. The proposed method can generate unsigned multipliers (or signed multipliers) based on the Braun multiplier (or Baugh-Wooley multiplier). To demonstrate the effectiveness of the method, three different-scale quantized DNNs, including LeNet, AlexNet, and VGG16 with 8 × 8 unsigned multiplication and an adaptive least mean square (LMS)-based finite impulse response (FIR) filter with 16 × 16 fixed-point signed multiplication, are evaluated. In the DNN training process, a noise training technique is adopted to reduce the accuracy loss due to the approximation. When compared to the state-of-the-art approximate multipliers, the generated multipliers can achieve up to 26.4% and 27.1% product of power, delay, and area gains with negligible application-level performance loss in VGG16 and FIR applications, respectively. © 1993-2012 IEEE.

关键词： Impulse response

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Periodic Analysis of Adaptive LMS Filter in TIADC 15

Periodic Analysis of Adaptive LMS Filter in TIADC

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15th IEEE International Conference on asic, asicON 2023

作者： Li, Jiankun Lin, Zepeng Ye, Fan Fudan University College of Microelectronics Shanghai China Fudan University State Key Laboratory of ASIC and System Shanghai China

ISBN: (纸本)9798350312980

A periodic analysis of LMS adaptive filter in TI-ADC is presented. TI-ADC is a efficient technique to reach high sampling frequency but mismatches among different sub-ADCs influence its performance. LMS adaptive filter is a finite impulse response (FIR) filter which adapt itself to different inputs once implemented. To analyse SFDR performance of LMS filter in time domain, converged weigh vector and its analysis frequency domain are done theoretically and emulationally. Simulation shows that our theoretical analysis is consistent with the practical results that the useful range of SFDR performance is only negatively related to filter length if sampling frequency is constant. Further, it is concluded that there is a trade-off between maximum of SFDR in LMS filter and its useful range in terms of frequency. © 2023 IEEE.

关键词： adaptive filter LMS TI-ADC

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Automated Design Space Exploration of Coarse-Grained Reconfigurable Architecture via Bayesian Optimization 16

Automated Design Space Exploration of Coarse-Grained Reconfi...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Kuang, Huizhen Zheng, Su Wang, Lingli Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Due to high energy efficiency, runtime reconfigurability, and low hardware cost, coarse-grained reconfigurable architecture (CGRA) is promising in many rapid-evolving applications. Nevertheless, CGRA architecture design is an extremely costly task that requires searching a vast design space. We propose a fast automated design space exploration (DSE) algorithm based on Bayesian optimization (BO) to search the design space modeled by a black-box. Experimental results show that our approach significantly outperforms simulated annealing (SA) and genetic algorithm (GA). The optimized architecture has dramatic mapping performance improvements while saving the hardware area by 36% and 12% respectively compared with the optimized architectures by GA and SA. © 2022 IEEE.

关键词： Simulated annealing

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Integration of Droplet Transport and Mixing on EWOD 16

Integration of Droplet Transport and Mixing on EWOD

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Gao, Shang Rui, Xichuan Zhou, Jia Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Microdroplet transportation and mixing are indispensable functions in lab-on-chip applications. Additional components to conventional microfluidic platforms have solved the problem but with the big increase in the complexity of system integration. Here we propose an EWOD (Electrowetting on Dielectrics) design of driving electrode with a micro-barrier structure that enables the droplet mixing simultaneously along with the unidirectional transportation controlled by only two signals. The nesting asymmetrical electrodes not only provide the unidirectional driving pressure to the droplets, but also enhance the mixing of droplets by the specific micro-barrier structure through the curvilinear and fluctuating movement of the droplets. This design demonstrates a new approach to functional integration of EWOD microfluidic chips, which is of great significance in bioanalysis, especially in POCT (Point of Care Technology). © 2022 IEEE.

关键词： Drops

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Addressing and two-dimensional driving of droplets on single-sided continuous optoelectrowetting chip 16

Addressing and two-dimensional driving of droplets on single...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Liu, Enqing Wang, Cui Riaud, Antoine Zhou, Jia Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Digital microfluidics(DMF) represented by electrowetting on dielectrics(EWOD) has a broad application prospect in bioassay, chemical synthesis and drug discovery, but currently EWOD technology faces problems such as wiring bottleneck and complexity of droplet detection circuits. Optoelectrowetting(OEW) addresses the wiring bottleneck issue by using light pattern to control droplets. To date, light patterns have been designed by hand and have only allowed one dimensional manipulation. In this paper, we introduced a method using programmable optical patterns to modulate the electric field distribution on the chip, which realized two dimensional manipulation of droplet on the chip. At the same time, machine learning target detection algorithms YOLOv3 was used to accurately detection of droplets the self-addressing of light patterns. © 2022 IEEE.

关键词： Digital microfluidics

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Increasing the Post Halo Implantation Anneal Temperature for the Effective Improvement of Threshold Voltage Roll-off Induced by the Unique Non-uniform Boron Diffusion from the Embedded Source/Drain

Increasing the Post Halo Implantation Anneal Temperature for...

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2022 China Semiconductor Technology International Conference, CSTIC 2022

作者： Li, Run-Ling Jiang, Yu-Long School of Microelectronics Fudan University State Key Laboratory of Asic and System Shanghai200433 China

ISBN: (数字)9781665497589

ISBN: (纸本)9781665497589

The severe threshold voltage (Vt) roll-off is revealed for PMOSFETs with the embedded SiGe source/drain (eSiGe S/D) when the gate length decreases. The unique non-uniform boron diffusion into the channel region from eSiGe is found to be the main reason, which is intrinsically caused by the sigma-shaped trench. Lowering the growth temperature of eSiGe is widely adopted to solve the Vt roll-off issue but with a very complicated adjustment of eSiGe growth process. Without the change of eSiGe growth process, a post halo implantation anneal at a higher temperature before the S/D trench etching is proposed and demonstrated to be able to effectively improve the Vt roll-off too, providing a new way to suppress short channel effect. © 2022 IEEE.

关键词： Threshold voltage

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Construction of mesoporous silica-implanted tungsten oxides for selective acetone gas sensing

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Chinese Chemical Letters 2024年第11期35卷 492-498页

作者： Jichun Li Zhengren Wang Yu Deng Hongxiu Yu Yonghui Deng Xiaowei Cheng Kaiping Yuan Department of Chemistry Shanghai Stomatological Hospital&School of StomatologyState Key Laboratory of Molecular Engineering of PolymersShanghai Key Laboratory of Molecular Catalysis and Innovative MaterialsiCHEMFudan UniversityShanghai 200433China Frontier Institute of Chip and System State Key Laboratory of ASIC and SystemFudan UniversityShanghai 200433China State Key Lab of Transducer Technology Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Shanghai 200050China

As a key biomarker for noninvasive diagnosis of diabetes,the selective detection of trace acetone in exhaled gas using a portable and low-cost device remains a great *** metal oxide(SMO)based gas sensors have drawn signification attention due to their potential in miniaturization,user-friendliness,high cost-effectiveness and selective real-time detection for noninvasive clinical ***,we propose a one-pot solvent evaporation induced tricomponent co-assembly strategy to design a novel ordered mesoporous SMO of silica-implanted WO_(3)(Si O_(2)/WO_(3))as sensing materials for trace acetone *** controlled co-assembly of silicon and tungsten precursors and amphiphilic diblock copolymer poly(ethylene oxide)-block-polystyrene(PEO-b-PS),and the subsequent thermal treatment enable the local lattice disorder of WO_(3)induced by the amorphous silica and the formation of ordered mesoporous Si O_(2)/WO_(3)hybrid walls with a unique metastableε-phase WO_(3)*** obtained mesoporous SiO_(2)/WO_(3)composites possess highly crystalline framework with large uniform pore size(12.0-13.3 nm),high surface area(99-113 m^(2)/g)and pore volume(0.17-0.23 cm^(3)/g).Typically,the asfabricated gas sensor based on mesoporous 2.5%Si O_(2)/WO_(3)exhibits rapid response/recovery rate(5/17 s),superior sensitivity(R_(air)/R_(gas)=105 for 50 ppm acetone),as well as high selectivity towards *** limit of detection is as low as 0.25 ppm,which is considerably lower than the thresh value of acetone concentration(>1.1 ppm)in the exhaled breath of diabetic patients,demonstrating its great prospect in real-time monitoring in diabetes ***,the mesoporous 2.5%Si O_(2)/WO_(3)sensor is integrated into a wireless sensing module connected to a smart phone,providing a convenient real-time detection of acetone.

关键词： Mesoporous materials ε-Tungsten oxide Silica-implanted Acetone sensing Real-time detection

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Integrating 2D layered materials with 3D bulk materials as van der Waals heterostructures for photodetections:Current status and perspectives

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InfoMat 2023年第10期5卷 1-31页

作者： Weijie Liu Yiye Yu Meng Peng Zhihua Zheng Pengcheng Jian Yang Wang Yuanchen Zou Yongming Zhao Fang Wang Feng Wu Changqing Chen Jiangnan Dai Peng Wang Weida Hu Wuhan National Laboratory for Optoelectronics Huazhong University of Science and TechnologyWuhanthe People's Republic of China State Key Laboratory of Infrared Science and Technology Shanghai Institute of Technical PhysicsChinese Academy of SciencesShanghaithePeople's Republic of China State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghaithe People's Republic of China

In the last decade,two-dimensional layered materials(2DLMs)have been drawing extensive attentions due to their unique properties,such as absence of surface dangling bonds,thickness-dependent bandgap,high absorption coeffi-cient,large specific surface area,and so *** the high-quality growth and transfer of wafer-scale 2DLMs films is still a great challenge for the commerciali-zation of pure 2DLMs-based ***,the material growth and device fabrication technologies of three-dimensional(3D)semiconductors photodetectors tend to be gradually ***,the further improvement of the photodetection performance is limited by the difficult heterogeneous inte-gration or the inferior crystal quality via ***,2D/3D van der Waals heterostructures(vdWH)combine the advantages of the two types of materials simultaneously,which may provide a new platform for developing high-performance optoelectronic ***,we first discuss the unique advantages of 2D/3D vdWH for the future development of photodetection field and simply introduce the structure categories,working mechanisms,and the typical fabrication methods of 2D/3D vdWH ***,we outline the recent progress on 2D/3D vdWH-based photodetection devices integrating 2DLMs with the traditional 3D semiconductor materials,including Si,Ge,GaAs,AlGaN,SiC,and so ***,we highlight the current challenges and pros-pects of heterointegrating 2DLMs with traditional 3D semiconductors toward photodetection applications.

关键词： photodetectors three-dimensional semiconductors two-dimensional layered materials vander Waals heterostructures

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An artificial neural network chip based on two-dimensional semiconductor

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Science Bulletin 2022年第3期67卷 270-277页

作者： Shunli Ma Tianxiang Wu Xinyu Chen Yin Wang Hongwei Tang Yuting Yao Yan Wang Ziyang Zhu Jianan Deng Jing Wan Ye Lu Zhengzong Sun Zihan Xu Antoine Riaud Chenjian Wu David Wei Zhang Yang Chai Peng Zhou Junyan Ren Wenzhong Bao State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China State Key Laboratory of ASIC and System School of Information Science and TechnologyFudan UniversityShanghai 200433China Shenzhen Sixcarbon Technology Shenzhen 518106China School of Electronic and Information Engineering Soochow UniversitySuzhou 215006China Department of Applied Physics The Hong Kong Polytechnic UniversityHung HomKowloonHong KongChina

Recently,research on two-dimensional(2D)semiconductors has begun to translate from the fundamen-tal investigation into rudimentary functional *** this work,we unveil the first functional MoS2 artificial neural network(ANN)chip,including multiply-and-accumulate(MAC),memory and activation function *** MoS2 ANN chip is realized through fabricating 818 field-effect transistors(FETs)on a wafer-scale and high-homogeneity MoS2 film,with a gate-last process to realize top gate structured FETs.A 62-level simulation program with integrated circuit emphasis(SPICE)model is utilized to design and optimize our analog ANN *** demonstrate a practical application,a tactile digit sensing recognition was demonstrated based on our ANN *** training,the digit recognition rate exceeds 97%.Our work not only demonstrates the protentional of 2D semiconductors in wafer-scale inte-grated circuits,but also paves the way for its future application in AI computation.

关键词： MoS_(2) Two-dimensional(2D)FETs Artificial neural network(ANN) Multiply-and-accumulate(MAC) Circuits

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A Valuable and Low-Budget Process Scheme of Equivalized 1 nm Technology Node Based on 2D Materials

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Nano-Micro Letters 2025年第8期 302-313页

作者： Yang Shen Zhejia Zhang Zhujun Yao Mengge Jin Jintian Gao Yuhan Zhao Wenzhong Bao Yabin Sun He Tian College of Integrated Circuit Science and Engineering Shanghai Key Laboratory of Multidimensional Information ProcessingEast China Normal University State Key Laboratory of ASIC and System School of MicroelectronicsFudan University Institute of Microelectronics and Beijing National Research Center for Information Science and Technology (BNRist) Tsinghua University Shaoxin Laboratory

Emerging two-dimensional（2D） semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness. As the stacking process advances, the complexity and cost of nanosheet field-effect transistors（NSFETs） and complementary FET（CFET） continue to rise. The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems（IRDS）(2022, https://irds. ieee. org/), but not publicly confirmed, indicating that more possibilities still exist. The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area, power consumption and speed. In this study, a comprehensive framework is built. A set of MoS2NSFETs were designed and fabricated to extract the key parameters and performances. And then for benchmarking, the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device footprint. Under these conditions, the frequency of ultra-scaled 2D-NSFET is found to improve by 36% at a fixed power consumption. This work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes, i.e., “2D eq 1 nm” nodes. At the same time, thanks to the lower characteristic length of 2D semiconductors, the miniaturized 2D-NSFET achieves a 28% frequency increase at a fixed power consumption. Further, developing a standard cell library, these devices obtain a similar trend in 16-bit RISC-V CPUs. This work quantifies and highlights the advantages of 2D semiconductors in advanced nodes, offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.

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