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Characterization and Modeling of MOSFET Series Resistance Down to 4 K

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY 2025年 13卷 297-302页

作者： Lin, Yuhuan Ma, Zhizhao Li, Shilong Wen, Tianyue Zhou, Yuxuan Su, Hao Zhou, Shenghua Lin, Longyang Li, Yida Chen, Kai Southern Univ Sci & Technol Sch Microelect Shenzhen 518055 Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI IME ECE FST Macau Macao Peoples R China

MOSFET parasitic series resistance (R-SD) is an important parameter when channel length scales down. This paper presents a systematic study of R-SD extracted from the mobility constant method down to 4 K. For the first time, the anomalous behavior of R-SD with temperature lowering is interpreted and modeled by combined effects of dopant freeze-out and mobility. Excellent fit between the standard N/P-MOSFET measurement data and this model for 40 nm bulk device from leading foundry is shown from 300 K to 4 K. In addition, R-SD change with width scaling combined with temperature effects is also discussed.

关键词： Resistance MOSFET circuits Logic gates MOSFET Semiconductor device modeling Junctions Electrical resistance measurement Cryogenics Conductivity Systematics Series resistance R-SD cryogenic extraction model

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Fully Symmetrical Obfuscated Interconnection and Weak-PUF-Assisted Challenge Obfuscation Strong PUFs Against Machine-Learning Modeling Attacks

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IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY 2024年 19卷 3927-3942页

作者： Xu, Chongyao Zhang, Litao Mak, Pui-In Martins, Rui P. Law, Man-Kay Univ Macau Inst Microelect Fac Sci & Technol FST ECE State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Fac Sci & Technol FST ECE Dept Elect & Comp Engn Macau Peoples R China Univ Macau Fac Sci & Technol FST ECE Dept State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China

In this paper, we propose a fully symmetrical obfuscated-interconnection PUF (SOI PUF), which contains n delay stages with each stage having 4k obfuscated interconnections for resisting machine learning (ML)-based modeling attacks. All the delay stages contribute to k PUF primitives while achieving a 20x increase in the number of possible interconnections with the same hardware resources over similar prior arts. The SOI PUF mathematical model also theoretically demonstrates the large number of nonlinear matrix multiplications for resisting ML-based modeling attacks. We further exploit parallel weak PUF cells and propose the challenge-obfuscated SOI PUF (cSOI PUF), which can effectively prevent adversaries from bypassing unknown interconnections through reverse engineering (RE) attacks. The proposed SOI PUF and cSOI PUFs are evaluated by both software simulation and FPGA measurements. Without requiring a large k as in the existing PUF architectures, the simulation results demonstrate that the proposed SOI and cSOI PUFs can achieve a similar to 50% prediction accuracy for k >= 3, even when facing ML attacks using 5-hidden-layer Artificial Neural Network (ANN) with 40M training CRPs. Furthermore, the proposed (64,2/4/6/8)-SOI PUF and (64,2/4/6/8)-cSOI PUF implemented using Xilinx Artix-7 FPGA can both achieve a measured reliability and uniformity of >94% and similar to 50%, respectively. Depending on the value of k , the uniqueness ranges from 29.1% to 42.7% for SOI PUFs, and further improves to similar to 50% for cSOI PUFs. The resilience against reliabiltiy-based modeling attacks, Probably Approximately Correct (PAC) attacks and RE-based modeling attacks will also be discussed.

关键词： Physical unclonable function (PUF) machine learning (ML) modeling attack symmetrical obfuscated interconnection (SOI) challenge obfuscation reverse engineering (RE)

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Rapid Discovery of Gas Response in Materials Via Density Functional Theory and Machine Learning

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Energy & Environmental Materials 2025年第1期8卷 164-172页

作者： Shasha Gao Yongchao Cheng Lu Chen Sheng Huang School of Materials Science and Physics China University of Mining and TechnologyXuzhou 221116China State-Key Laboratory of Analog and Mixed-Signal VLSI IMEUniversity of MacaoMacao 999078China

In this study,a framework for predicting the gas-sensitive properties of gas-sensitive materials by combining machine learning and density functional theory(DFT)has been *** framework rapidly predicts the gas response of materials by establishing relationships between multisource physical parameters and gas-sensitive *** order to prove its effectiveness,the perovskite Cs_(3)Cu_(2)I_(5) has been selected as the representative *** physical parameters before and after the adsorption of various gases have been calculated using DFT,and then a machine learning model has been trained based on these *** studies have shown that a single physical parameter alone is not enough to accurately predict the gas sensitivity of ***,a variety of physical parameters have been selected for machine learning,and the final machine learning model achieved 92%accuracy in predicting gas *** is important to note that although there have been no previous reports on the response of Cs_(3)Cu_(2)I_(5) to hydrogen sulfide,the resulting model predicts the gas response of H2S;it is subsequently confirmed *** method not only enhances the understanding of the gas sensing mechanism,but also has a universal nature,making it suitable for the development of various new gas-sensitive materials.

关键词： density functional theory gas-sensitive materials machine learning

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A VCF-Step-Reconfigurable Continuously Scalable-Conversion-Ratio Switched-Capacitor Converter

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IEEE JOURNAL OF SOLID-state CIRCUITS 2025年第2期60卷 626-637页

作者： Wang, Yuanfei Huang, Mo Chen, Qiujin Martins, Rui P. Lu, Yan Univ Macau Dept Elect & Comp Engn ECE State Key Lab Analog & Mixed Signal VLSI Fac Sci & Technol FSTInst Microelect Macau Peoples R China

This article proposes a V-CF -step-reconfigurable continuously scalable-conversion-reconfigurable CSC (RCSC). We first analyze the working principle of the conventional conversion-ratio SC (CSC) converter and why it has reduced efficiency over a wide voltage conversion ratio (VCR) range. Then, the proposed RCSC reconfigures and thus equalizes the step size of the flying capacitor C-F voltage (V-CF) according to the VCR. This maximizes efficiency over a wider range of VCRs, with limited circuitry complexity. Subsequently, we propose a gate control signal generation scheme that significantly reduces the cost overhead of the reconfiguration. The proposed RCSC can be used in either step-up or step-down mode and is compatible with maximum power point tracking (MPPT) in energy harvesting systems. Implemented with a 65-nm CMOS process, the proposed RCSC reaches a 90% peak efficiency using 34 V-CF steps and the widest normalized VCR range with > 75% efficiency.

关键词： Continuously scalable-conversion-ratio maximum power point tracking (MPPT) reconfigurable VCF step switched-capacitor (SC) converter wide voltage conversion ratio (VCR) range

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Reactive oxygen species and nitric oxide scavenging nanoparticles alleviating rheumatoid arthritis through adjusting the seeds and growing soils

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Acta Pharmaceutica Sinica B 2023年第12期13卷 5016-5029页

作者： Peng Hua Ruifeng Liang Yanbei Tu Yuying Yin Man-Kay Law Meiwan Chen State Key Laboratory of Quality Research in Chinese Medicine Institute of Chinese Medical SciencesUniversity of MacaoMacao SARChina State Key Laboratory of Analog and Mixed-Signal VLSI IME and FST-ECEUniversity of MacaoMacao SARChina

Normalizing inflamed soils including reactive oxygen species(ROS),nitric oxide(NO),cellfree DNA,and regulating infammation-related seeds such as macrophages,neutrophils,fibroblasts,represent a promising strategy to maintain synovial tissue homeostasis for rheumatoid arthritis(RA)***,ROS scavenging amphiphilic block copolymer PEGylated bilirubin and NO-scavenging PEGylated o-phenylenediamine were fabricated to self-assemble into a dually responsive nanoparticle loaded with JAK inhibitor notopterol(Not@BR/oPDA-PEG,NBOP NPs).The simultaneous ROS and NO depletion combined with JAK-STAT pathway inhibition could not only promote M2 polarization to reduce further ROS and NO generation,but also decrease cytokines and chemokines to prevent immune cell ***,NBOP NPs responded to high level ROS and NO,and disintegrated to release notopterol in inflamed joints as the hydrophobic heads BR and oPDA were transformed into hydrophilic *** released notopterol could inhibit the JAK-STAT pathway of infammatory cells to reduce the secretion of pro-inflammatory cytokines and *** strategy represented an effective way to regulate RA soils and seeds through breaking the positive feedback loop of inflammation aggravation,achieving an excellent anti-RA efficacy in a collagen-induced arthritis rat *** together,our work offered a reference to adjust RA soils and seeds for enhanced RA treatment.

关键词： Bilirubin o-Phenylenediamine Notopterol ROS and NO scavenging JAK-STATpathway Anti-inflammatory Cartilage protection Rheumatoid arthritis

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A 24-V-Input Highly Integrated Interleaved-Inductor Multiple Step-Down Hybrid DC-DC Converter With Inherent Current Equalization Characteristics

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IEEE JOURNAL OF SOLID-state CIRCUITS 2024年第9期59卷 2895-2906页

作者： Zhang, Xiongjie Zhao, Anyang Ma, Qiaobo Jiang, Yang Law, Man-Kay Martins, Rui P. Mak, Pui-In Univ Macau Inst Microelect IME State Key Lab Analog & Mixed Signal VLSI Fac Sci & Technol FST Taipa Macau Peoples R China Univ Macau Fac Sci & Technol FST Dept ECE Taipa Macau Peoples R China

This article presents a highly integrated hybrid dc-dc converter with a 24-V input, employing the interleaved-inductor multiple step-down (IL-MSD) topology. The proposed design ensures symmetric power-stage operations, addressing inductor current ( I-L) imbalance without complex regulation control. It also optimizes current distribution among internal conduction branches, reducing conduction losses and input capacitor requirements. In addition, we propose an on-chip gate-driving scheme utilizing a high-voltage (HV) floating current (HVFC) source and HV charge storage technique, eliminating external bootstrap capacitors and extra HV supplies. Fabricated in a 180-nm BCD process, the converter chip integrates all-N-type power switches, gate drivers (GDs), startup/pre-charge circuits, and control blocks within a 4.7-mm $<^>{2}$ footprint. Using two 1- $\mu$ H compact inductors and four 1- $\mu$ F flying capacitors, the converter regulated a 1-3.5-V output from a 24-V input with a peak efficiency of 90.4% under a 1.2-A load. The maximum load current reaches 5 A with an 82% efficiency. The achieved on-chip and overall power densities are 3.51 and 0.62 W/mm(3) , respectively.

关键词： Switches Topology Inductors Video recording Power system measurements Density measurement Capacitors DC-DC converter fully symmetric high step-down hybrid topology interleaved inductor on-chip gate driver (GD)

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A 0.004-mm² 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS

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IEEE JOURNAL OF SOLID-state CIRCUITS 2023年第11期58卷 3179-3193页

作者： Zhang, Chenghao Wei, Jiangbo Chen, Yong Liu, Maliang Yang, Yintang Xidian Univ Sch Microelect Xian Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI IME & ECE FST Taipa Macao Peoples R China

This article reports an area-power-efficient 7-bit 2-GS/s time-domain analog-to-digital converter (TD-ADC) based on a gated ring oscillator (GRO). A pulse generator (PG) with the dead-zone elimination technique is devised for maximizing the linearity of the gated signal. The GRO-based time-todigital converter employs a robust interpolation that effectively increases the interpolation accuracy of the GRO and improves the overall resolution. Also, a phase-tracking sampling generator is developed to suppress the leakage effect of the GRO and enhance the energy efficiency of the time-to-digital conversion. Moreover, a digital-assisted calibration technique is designed to eliminate the quantization error caused by the time-folding offset. The TD-ADC prototype is fabricated in a 28-nm CMOS process with an active area of 0.004 mm(2). It scores a measured peak SNDR of 38.63 dB and an SFDR of 50.66 dB at the conversion rate of 2 GS/s, along with the figure of merit (FoM) of 31.4 fJ/conversion step.

关键词： analog-to-digital converter (ADC) calibration CMOS folding gated ring oscillator (GRO) interpolation pulse generator (PG) time domain (TD) voltage domain (VD)

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A 0.012-mm² 0.244-pJ/bit successive approximation register analog-to-digital converter-based true random number generator for Internet of Things applications in a 65-nm complementary metal-oxide-semiconductor

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2024年第12期52卷 6028-6055页

作者： Cheng, Kai Chen, Yong Stefano, Crovetti Paolo Martins, Rui P. Mak, Pui-In Univ Macau State Key Lab Analog & Mixed Signal VLSI & IME ECE Taipa Macau Peoples R China Politecn Torino Dept Elect & Telecommun DET Turin Italy

This paper proposes a true random number generator (TRNG) based on a successive approximation register (SAR) analog-to-digital converter (ADC). A top-plate sampling SAR ADC structure and a new MSB-isolation switch scheme (MISS) are combined to achieve low-power operation and small area occupancy at the same time. When the SAR ADC has completed its conversion, a secondary firing of the comparator measures the remaining signal. This 1-bit quantized residue serves as the true random sequence, thus eliminating the need for extra circuitry in the TRNG. A 65-nm prototype of the proposed TRNG was found to occupy an area of 0.012 mm(2) and successfully passed all the National Institute of Standards and Technology (NIST) tests without post-processing. It achieved a figure-of-merit of 0.244 pJ/bit for a 1 Mb/s random sequence with a 0.8-V power supply. Its resilience to power noise injection attacks was also verified.

关键词： analog-to-digital converter (ADC) capacitive digital-to-analog converters (CDACs) cryptography entropy National Institute of Standards and Technology (NIST) successive approximation register (SAR) thermal noise true random number generator (TRNG)

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A High-Efficiency Low-Cost Multi-Antenna Energy Harvesting System With Leakage Suppression

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IEEE JOURNAL OF SOLID-state CIRCUITS 2024年第9期59卷 2995-3007页

作者： Zhang, Zhaobo Zhan, Chenchang Zhao, Shuangxing Law, Man-Kay Southern Univ Sci & Technol Sch Microelect Shenzhen 518055 Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI IME & FST Macau Peoples R China

This article presents a multi-antenna RF energy harvester (MARFEH) with leakage suppression to achieve high output power and avoid the effects of interference and blind spots in the room, and all the RF rectifiers share only one buffering capacitor to achieve low cost. The proposed leakage-suppressed rectifier utilizing adaptive V-TH compensation (AVC) and an RF switch can achieve self-turned-off operation to prevent power leakage due to power imbalance among all the parallel-connected rectifiers. The RF harvester also exhibits maximum power point tracking (MPPT) and a 1.8-V regulated output through a boost dc-dc converter. The MPPT is realized by an optimized on-chip perturb and observe (P&O) controller and achieves sub-mu W system control power consumption. Meanwhile, MPPT is used to estimate the RF input power to drive the AVC circuit to improve rectifier efficiency and assist in leakage suppression. The chip prototype was designed in a 180-nm CMOS process and occupies an area of 0.89 mm(2). Using a single antenna with AVC and MPPT enabled, the proposed harvester achieves a power conversion efficiency (PCE) of about 37% and 38% at an input power of -10 and +4 dBm, respectively. The measured peak PCE is 44% at -0.3 dBm. Wireless tests show that the peak output power at different test conditions is significantly improved when the number of antennas increases from 1 to 2 and to 3. Furthermore, an accurate rectifier model is presented to significantly shorten the system simulation time of the rectifier-dc-dc two-stage topology.

关键词： Boost dc-dc converter cold start Internet of Things (IoT) maximum power point tracking (MPPT) multi-antenna RF energy harvesting

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Comprehensive analysis of MOSFET threshold voltage extraction method considering DIBL effect from 300 K down to 10 K

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SOLID-state ELECTRONICS 2025年 224卷

作者： Ma, Zhizhao Su, Hao Lin, Yuhuan Zhou, Shenghua Zhou, Feichi Liu, Xiaoguang Lin, Longyang Li, Yida Chen, Kai Southern Univ Sci & Technol SUSTech Shenzhen 518055 Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI IME ECE FST Macau Peoples R China Int Quantum Acad Shenzhen 518048 Peoples R China

It is well known that different threshold voltage (Vth) extraction methods exhibit inconsistencies with respect to different drain voltage (Vd). This inconsistency becomes disruptive when temperature is considered for cryogenic applications such as quantum computing. This investigation examines various V th extraction methods from room down to cryogenic temperatures, with a particular emphasis on how different Vd values combined with extraction methods behave as temperature decreases. For the first time, we find that the square root Id method maintains consistency regardless of V d , from 300 K all the way down to 10 K is identified. This provides a good insight into how the Drain-Induced Barrier Lowering (DIBL) effect changes with temperature, and positions the square root Id method as a reliable tool for V th extraction in cryogenic temperature.

关键词： Threshold Voltage Extraction Method Cryogenic DIBL

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