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2024 IEEE Asian Solid-state Circuits Conference, A-SSCC 2024

作者： Xing, Kai Zhu, Yan Martins, Rui Paulo Chan, Chi-Hang State-Key Laboratory of Analog and Mixed Signal VLSI DECE FST University of Macau China

ISBN: (纸本)9798350376326

With the advent of WLAN technologies, over 320 MHz BW and > 65dB DR ADCs become indispensable to support newly developed WiFi standards. Three classic solutions can reach the said targets but involve various compromises (Fig. 1 top). CT MASH ADCs [1] rely on a relatively high OSR (7) as well as NS order to accommodate the adequate noise spectral density (NSD), limiting the energy efficiency. The CT pipeline (PIPE) ADC [2-3] obviates the feedback loop and its 1st stage energy effectively provides preliminary quantization, residue generation, amplification, and filtering. However, the backend CT quantization can be power-hungry [2] [4]. The DT NS pipeline ADC offers a low-power alternative [5] but loses the intrinsic anti-aliasing (AA) ability from its CT counterparts. This work hybridizes CT and DT NS PIPE, gaining the pros from the CT PIPE front-end and DT PIPE backend. Together with the Single amplifier biquad (SAB) - Residue Amplifying Filter (RAF) and NS TD-QTZ, the C/DT PIPE ADC demonstrates superior energy efficiency over CT MASH ADCs with 320MHz BW. © 2024 IEEE.

关键词： Anti-aliasing

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A Switchless Dual-core Triple-Mode VCO Achieving 7.1-to-15.7 GHz Frequency Tuning Range and 202.1 dBc/Hz Peak FoM at 3.7 Kelvin

A Switchless Dual-core Triple-Mode VCO Achieving 7.1-to-15.7...

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IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

作者： Wu, Yue Peng, Yatao Huo, Benhao Yin, Jun Martins, Rui P. Mak, Pui In Univ Macau State Key Lab Analog & Mixed Signal VLSI IME ECE FST Taipa Macao Peoples R China Univ Lisbon Inst Super Tecn Lisbon Portugal

ISBN: (纸本)9798350359480;9798350359473

We reported a dual-core triple-mode voltage-controlled oscillator (VCO) to adapt to the low power consumption and large frequency tuning range (FTR) of the signal source in quantum interface systems. We proposed using only magnetic and inductive tuning elements for resonance splitting to construct the VCO's triple-mode LC tank. This avoids the FTR sacrifice when using a conventional capacitive tuning element to build the multi-mode tank. To reduce the power consumption of the negative transconductance (-G(M)) cells in the multicore multi-mode VCO, we proposed a structure that provides a triple oscillating mode with only two -G(M) cores. In addition, to overcome the deterioration of phase noise (PN) due to the switch-on resistances, we introduced a switching -G(M) technique for mode selection without using the MOSFET switches. The wideband VCO was specifically designed for cryogenic operation, utilizing a 28 nm CMOS technology. The measured results demonstrate an FTR of 7.1-15.7 GHz (75.4%) and a peak figure-of-merit (FoM) of 202.1 dBc/Hz at 3.7 Kelvin.

关键词： VCO mode-switching switch-less cryogenic CMOS quantum interface frequency tuning range

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Functionalized PAMAM constructed nanosystems for biomacromolecule delivery

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BIOMATERIALS SCIENCE 2023年第5期11卷 1589-1606页

作者： Wong, Ka Hong Guo, Zhaopei Law, Man-Kay Chen, Meiwan Univ Macau Inst Chinese Med Sci State Key Lab Qual Res Chinese Med Macau Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI IME & FST ECE Macau Peoples R China

Polyamidoamines (PAMAMs) are a class of dendrimer with monodispersity and controlled topology, which can deliver biologically active macromolecules (e.g., genes and proteins) to specific regions with high efficiency and minimum side effects. In detail, PAMAMs can be functionalized easily by core modification or surface amendment to encapsulate a wide range of biomacromolecules. Besides, self-assembled, cross-linked and hybrid PAMAMs with customized therapeutic purposes are developed as delivery vehicles, which makes PAMAMs promising for biomacromolecule therapy. In this review, we comprehensively summarize the application of PAMAMs in biomacromolecule delivery from the synthesis of functionalized PAMAM carriers to the development of PAMAM-based drug delivery systems. The underlying strategies for PAMAM functionalization and assembly are first systematically discussed, and then the current applications of PAMAMs for biomacromolecule delivery are reviewed. Finally, a brief perspective on the further applications of PAMAMs concludes, aiming to provide insights into developing PAMAM-based biomacromolecule delivery systems.

关键词： Nanosystems

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A 27 W Wireless Power Transceiver With Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control

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IEEE JOURNAL OF SOLID-state CIRCUITS 2024年第6期59卷 1782-1793页

作者： Ma, Xiaofei Ki, Wing-Hung Lu, Yan Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Peoples R China Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Fac Sci & Technol FST ECE Macau Peoples R China Univ Macau Fac Sci & Technol FST ECE Dept Elect & Comp Engn Macau Peoples R China

This work presents a reconfigurable single-stage regulated Class-E (SSRE) wireless power transceiver that delivers 27 W for wireless charging at 6.78 MHz. The power stage of the transmitter merges a buck and a Class-E power amplifier (PA) into one conversion stage, saving one inductor and one capacitor with improved system efficiency. Instead of using a bulky external impedance tuning block to ensure a 50% duty cycle operating point, the proposed Class-E zero-voltage switching (ZVS) controller allows the Class-E stage to work at an adaptive duty cycle without an off-chip tuning circuit. The high voltage and high current stress of the Class-E stage is handled by a GaN transistor, the driver of which uses an NMOS transistor for the high-side switch that realizes a rising edge of 2.8 ns with no overshoot. For directly sensing high voltage without using a resistor divider, an HV-NMOS shielded push-pull comparator is designed. An adaptive dead time control based on a sample-and-hold (S/H) feedback loop is proposed to reduce reverse conduction and recovery loss of the buck stage. The proposed solution demonstrates good trade-off among power level, efficiency, and power density. The SSRE WPT system delivers a maximum dc output power of 27 W with an end-to-end (E2E) efficiency of 63.0% if the receiver uses a traditional passive rectifier. The peak E2E efficiency of 80.0% is achieved at dc output power of 9.5 W;furthermore, in a two-chip differential transmitter configuration, the maximum output power reaches 45 W, and the maximum E2E efficiency is 83.7%.

关键词： AC-DC adaptive dead time dc-ac device-to device (D2D) GaN driver power amplifier (PA) rectifier single stage regulation wireless fast charging wireless power transfer zero-voltage switching (ZVS)

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High-Efficiency Ultrasound Energy Harvesting Interface With Auto-Calibrated Timing Control From-25 ^°C to 85 ^°C

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IEEE JOURNAL OF SOLID-state CIRCUITS 2025年第3期60卷 871-882页

作者： Zhao, Guangshu Xie, Chao Wang, Chenxi Zhang, Milin Law, Man-Kay Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau FST ECE Macau Peoples R China Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China

This work presents a high-efficiency ultrasound energy harvesting interface with auto-calibrated timing control, featuring: 1) the proposed C(P )auto-calibration, consisting of the half bias-flip time ( t(half) ) detection and adaptive closed-loop time calibration (ACTC) to improve the system's robustness against piezoelectric transducer (PZT) materials and environmental variations;2) the proposed charge recycling (CR) bootstrapping driver to reduce conduction loss and improve the C(P )auto-calibration accuracy as well as the peak voltage flipping efficiency ( eta flip );and 3) the proposed coarse detection and fine calibration technique to eliminate the inherent timing offset and increase the acceptable input excitation frequency range. The fabricated chip prototype in 0.18- mu m silicon on insulator (SOI) CMOS process can adapt to both PZT5A (nominal C-P similar to 114 pF) and PZT5H (nominal C-P similar to 190 pF) and is capable of operating over a wide temperature range from - 25 degrees C to 85 degrees C. The proposed C(P )auto-calibration and CR bootstrapping driver can improve the eta flip to as high as 93.6% at an output power of 496.6 mu W. With the proposed coarse detection and fine calibration technique, this work demonstrates a high measured peak power conversion efficiency (PCE) of 94.5%, corresponding to a similar to 23% improvement when compared with the prior ultrasound energy harvesting interface while achieving a favorable figure of merit (FoM) of 8.13 x

关键词： Ultrasonic imaging Timing Lead zirconate titanate Rectifiers Energy harvesting Power generation Calibration Temperature measurement Delays Accuracy Adaptive time control auto-calibration bias-flip interface energy harvesting high efficiency piezoelectric transducer (PZT) ultrasound

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A 90-to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2023年第4期51卷 1530-1547页

作者： Wang, Xi Wei, Dong Zhang, Zhiyang Wu, Tianxiang Chen, Xu Chen, Yong Ren, Junyan Ma, Shunli Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI & IME ECE Macau Peoples R China

In this paper, a broadband superheterodyne receiver (RX) front-end for millimeter-wave (mm-Wave) imaging radar is presented. Realized in 28-nm CMOS technology, the proposed RX incorporates a wideband low-noise amplifier (LNA), double-balanced passive mixers for the dual down-conversion, a differential power divider, a differential intermediate frequency filters, a current-mode-logic divider-by-2, and a local oscillator buffers. Wideband technique and layout optimization are taken into consideration in the RX. A four-stage LNA is devised to realize the high gain and low noise figure (NF) with a common-gate input stage and three pseudodifferential common-source stages. Optimized transistor layout and capacitor neutralization technique are developed to improve gain and noise performance. Transformer-based matching networks with the peak-staggered technique are adopted in the LNA to achieve a flatter gain response with a wider bandwidth (BW). The passive double-balanced mixers are implemented with a highly symmetrical layout for broadband down-conversion. Simulation results show that the mm-Wave RX front-end exhibits a BW ranging from 90 to 115 GHz. The simulated NF of our RX is 4.7 dB at 86 GHz. With a supply voltage of 1 V, the presented RX consumes 88.2-mW power and occupies a chip size of 1.6 x 0.5 mm(2) including all the testing pads. The proposed RX is suitable for W-band imaging systems.

关键词： imaging system low-noise amplifier (LNA) peak-staggered matching technique superheterodyne receiver (RX) symmetrical-layout mixer transistor-layout optimization W-band wideband

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A 124-to-152-GHz Power Amplifier Exploiting Chebyshev-Type Two-Section Wideband and Low-Loss Power-Combining Technique in 28-nm CMOS

A 124-to-152-GHz Power Amplifier Exploiting Chebyshev-Type T...

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作者： Zhang, Jincheng Wang, Yujia Chen, Yong Ren, Junyan Ma, Shunli Fudan University State Key Laboratory of Asic and System Shanghai200433 China University of Macau State-Key Laboratory of Analog and Mixed-Signal Vlsi and IME/ECE-FST China

This article presents a high-power wideband power amplifier (PA) with a four-way power-combining technique for $D$ -band high-resolution radar. The power combiner is based on a two-section Chebyshev impedance converter to achieve a large bandwidth (BW) and is realized with slow wave coplanar waveguides (S-CPWs) to reduce the insertion loss and chip area. Therefore, our developed technique can provide broadband and low-loss power-combining scheme in a very compact size. A high-power PA with four-way combining has been fabricated in a 28-nm CMOS bulk technology. The unit PA uses low- $k$ transformer-based coupled-resonator networks to realize wideband matching. The measured results of the PA prototype demonstrate the peak gain of 22.6 dB, the saturated output power of 16.2 dBm, and the peak power added efficiency of 8.6% at 135 GHz with a 3-dB BW of 28 GHz from 124 to 152 GHz. Meanwhile, the total area of this PA die is merely 0.66 $\times $ 0.73 mm. © 1963-2012 IEEE.

关键词： Power amplifiers

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A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (vlsi) SYSTEMS 2023年第2期31卷 233-242页

作者： Wang, Yujia Zhang, Jincheng Chen, Yong Ren, Junyan Ma, Shunli Fudan Univ State Key Lab ASIC & Syst Shanghai 200433 Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI & IME ECE Macau Peoples R China

article presents a gallium nitride (GaN) wideband millimeter-wave power amplifier (PA) incorporating the Chebyshev matching technique. The theoretical design method of the wideband N-order Chebyshev matching network is proposed. Considering the insertion loss and circuit complexity, the second-order Chebyshev network is designed, which is implemented by transmission lines (TLs) and capacitors. Based on the designed matching network, a K-band PA is designed. Fabricated in a 250-nm GaN process, our PA scores the highest in-band gain of 23.8 dB at 23.6 GHz, 28% fractional bandwidth across 18.5-24.5 GHz, 32% peak power added efficiency (PAE), and 4.5-W saturated output power. The power density is 0.96 W/mm2 and the chip area is 2.4 x 1.95 mm(2).

关键词： Chebyshev matching technique gallium nitride (GaN) power added efficiency (PAE) power amplifier (PA) satellite communication wideband matching network

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A 0.016mm² Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2023年第10期70卷 3792-3796页

作者： Zhong, Junlin Yang, Xiaofeng Martins, Rui P. Zhu, Yan Chan, Chi-Hang Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Inst Microelect Dept ECE FST State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This brief presents a compact and power-efficient full ring-oscillator (RO)-based cascaded fractional-N PLL. The proposed cascaded PLL consists of a RO-based DLL and type-II PLL as the first and second stages, respectively. The first stage serves as a frequency multiplier that increases the operating frequency of the delta-sigma modulator (DSM) in the second stage, thereby suppressing its quantization noise. A burst-mode sampling (BMS) scheme is introduced to improve the phase noise (PN) of the frequency multiplier and achieves a PN multiplication factor removal. Implemented in a 28nm CMOS technology, the PLL prototype occupies a 0.016 mm(2) active area, achieving a 686 fs integrated rms jitter from 10KHz to 40MHz at a 4 GHz output frequency;while consuming 10.21mW with -233.6 dB FoMjitter. The measured fractional and reference spurs are -59.8 dBc and -54.5 dBc, respectively.

关键词： Fractional-N PLL ring VCO cascaded PLL burst-mode sampling (BMS) scheme

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Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal-oxide-semiconductor

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2024年第3期53卷 1253-1291页

作者： Yang, Chaowei Chen, Yong Cheng, Kai Stefano, Crovetti Paolo Martins, Rui P. Mak, Pui-In Univ Macau State Key Lab Analog & Mixed Signal VLSI IME & ECE Macau Peoples R China Politecn Torino Dept Elect & Telecommun DET Turin Italy Univ Lisbon Inst Super Tecn Lisbon Portugal

In this paper, to analyze the tuning range (TR) of transistors, we introduced two streamlined modeling approaches that can precisely predict the extent and direction of the TR. The first approach, known as the average DC (Id) method, employed a simplified circuit model to dissect transistor characteristics, enabling us to understand the general trajectory of the TR. The second approach involved the transient current Id (tc) method, which offers a nuanced portrayal of the transistor's real-world performance. By analyzing the current fluctuations within the transistor during transient states, its tuning capabilities could be more accurately ascertained. Further, this paper presents several designs for ultra-wide-tuning-range complementary metal-oxide-semiconductor (CMOS) voltage-controlled oscillators (VCOs) that employ a novel two-mode current-starved delay cell, featuring a tunable transistor-based current source for coarse frequency adjustment operating in synergy with a varactor for precise tuning. Using the 65-nm CMOS process, three prototype VCOs (Designs 2/3/4) based on the new cell and targeting different numbers of phases and performance were fabricated, thoroughly characterized, and compared with their traditional inverter-based counterpart (Design 1). Design 1 featured an inverter-based four-phase structure, with an output frequency range of 3.14-9.82 GHz, i.e., a radio frequency (RF) TR of 103%, with phase noise (PN) ranging from 137.7 to 132.1 dBc/Hz at an offset of 100 MHz, figure of merit with tuning range and area (FoMTA) varying from 200.7 to 205.1 dBc/Hz, and area of 0.0036 mm2. In contrast, Designs 2/3/4, based on the new delay cell, featured 8/3/4 phases, with output frequencies in the ranges of 1.14-9.17, 1.26-16.53, and 1.15-18.32 GHz, respectively, resulting in increased RF TRs of 155.8%, 171.7% and 176.4%, as well as PN at an offset of 100 MHz in the ranges of 142.1-138, 130.5-131.3, and 131.9-129.6 dBc/Hz, respectively. This yielded better FoM

关键词： Clock and data recovery (CDR) CMOS figure-of-merit (FoM) figure-of-merit with tuning and area (FoMTA) figure-of-merit with tuning range (FoMT) flicker (1/f) noise noise transfer phase noise (PN) phase-locked loop (PLL) quality factor switched-capacitor array (SCA) thermal noise transformer tuning range (TR) ultra-wide-tuning-range voltage-controlled oscillator (VCO)

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