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L: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs

IEEE Transactions on signal Processing 2023年 71卷 3229-3241页

作者： Wang, Bo Law, Man-Kay Schneider, Jens Hamad Bin Khalifa University College of Science and Engineering Doha34110 Qatar University of Macau State Key Laboratory of Analog and Mixed-Signal VLSI Institute of Microelectronics and FST-ECE 999078 China

While it becomes more challenging to improve the energy efficiency of incremental delta-sigma data converters (IDCs) from the analog circuit design perspective, we propose two novel linear reconstruction filters for IDCs to enhance their performance in a digital way, including the L${}_{\mathbf{2}}$min${}^{\mathbf{2}}$ filter and its symmetric version, the L${}_{\mathbf{2}}$min${}^{\mathbf{2s}}$ filter. Compared to the classical linear reconstruction filters, such as the cascade-of-integrators (CoI) and cascaded integrator-comb (CIC) filter (an implementation of sinc filter), the proposed filters can achieve efficient quantization and thermal noise suppression, with the lowest thermal noise penalty factor of 1.2 among the high-order linear reconstruction filters. In this paper, we present analytical, numerical, and experimental results to demonstrate the superior performance of the filters for first-order and second-order IDC output reconstruction. The proposed filters are hardware-friendly and example digital implementations in a standard complementary metal-oxide-semiconductor (CMOS) and field-programmable gate array (FPGA) platforms are included in this paper. © 1991-2012 IEEE.

关键词： Energy efficiency

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Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal-oxide-semiconductor

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2024年第3期53卷 1253-1291页

作者： Yang, Chaowei Chen, Yong Cheng, Kai Stefano, Crovetti Paolo Martins, Rui P. Mak, Pui-In Univ Macau State Key Lab Analog & Mixed Signal VLSI IME & ECE Macau Peoples R China Politecn Torino Dept Elect & Telecommun DET Turin Italy Univ Lisbon Inst Super Tecn Lisbon Portugal

In this paper, to analyze the tuning range (TR) of transistors, we introduced two streamlined modeling approaches that can precisely predict the extent and direction of the TR. The first approach, known as the average DC (Id) method, employed a simplified circuit model to dissect transistor characteristics, enabling us to understand the general trajectory of the TR. The second approach involved the transient current Id (tc) method, which offers a nuanced portrayal of the transistor's real-world performance. By analyzing the current fluctuations within the transistor during transient states, its tuning capabilities could be more accurately ascertained. Further, this paper presents several designs for ultra-wide-tuning-range complementary metal-oxide-semiconductor (CMOS) voltage-controlled oscillators (VCOs) that employ a novel two-mode current-starved delay cell, featuring a tunable transistor-based current source for coarse frequency adjustment operating in synergy with a varactor for precise tuning. Using the 65-nm CMOS process, three prototype VCOs (Designs 2/3/4) based on the new cell and targeting different numbers of phases and performance were fabricated, thoroughly characterized, and compared with their traditional inverter-based counterpart (Design 1). Design 1 featured an inverter-based four-phase structure, with an output frequency range of 3.14-9.82 GHz, i.e., a radio frequency (RF) TR of 103%, with phase noise (PN) ranging from 137.7 to 132.1 dBc/Hz at an offset of 100 MHz, figure of merit with tuning range and area (FoMTA) varying from 200.7 to 205.1 dBc/Hz, and area of 0.0036 mm2. In contrast, Designs 2/3/4, based on the new delay cell, featured 8/3/4 phases, with output frequencies in the ranges of 1.14-9.17, 1.26-16.53, and 1.15-18.32 GHz, respectively, resulting in increased RF TRs of 155.8%, 171.7% and 176.4%, as well as PN at an offset of 100 MHz in the ranges of 142.1-138, 130.5-131.3, and 131.9-129.6 dBc/Hz, respectively. This yielded better FoM

关键词： Clock and data recovery (CDR) CMOS figure-of-merit (FoM) figure-of-merit with tuning and area (FoMTA) figure-of-merit with tuning range (FoMT) flicker (1/f) noise noise transfer phase noise (PN) phase-locked loop (PLL) quality factor switched-capacitor array (SCA) thermal noise transformer tuning range (TR) ultra-wide-tuning-range voltage-controlled oscillator (VCO)

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A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors

A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32...

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2023 IEEE Symposium on vlsi Technology and Circuits, vlsi Technology and Circuits 2023

作者： Zhang, Minglei Cao, Yuefeng Zhu, Yan Chan, Chi-Hang Martins, R.P. University of Macau State-Key Laboratory of Analog and Mixed-Signal Vlsi Ime Macao China

ISBN: (纸本)9784863488069

This paper presents a 32× low-noise dynamic amplifier (DA) with a linearity-shifting technique, facilitating a 15b pipelined-SAR ADC with 80 dB SNR@DC. The linearity-shifted DA decouples the fundamental conflict between the noise and linearity in conventional DAs, rending a THD below -60dB at 0.8Vpp,diff output swing. Moreover, the reference voltages are stabilized by the cost-effective mounted-over-die bypass capacitors. The 60MS/s ADC achieves 95.8dB and 87.3dB SFDR with a DC and Nyquist input, respectively, and an input noise density of 10.2nV/√Hz. © 2023 JSAP.

关键词： Cost effectiveness

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Universal Stability Criterion for Type-I Sampling Phase-Locked Loops

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2023年第4期70卷 1351-1355页

作者： Huang, Yunbo Chen, Yong Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME ECE FST Macau Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This brief reports a universal stability criterion for the type-I sampling phase-locked loop (S-PLL). The linear-time- variant model predicts with precision a maximum phase margin that decreases linearly with the increasing loop bandwidth (BW), leading to a maximum achievable loop BW that is half of the reference frequency. We verified the derived theory through extensive simulations and will present a guide that is useful in the design and optimization of different S-PLL schemes.

关键词： Voltage-controlled oscillators Phase locked loops Circuit stability Mathematical models Stability criteria Behavioral sciences Amplitude modulation Type-I sampling phase-locked loop (S-PLL) sub-sampling PLL (SS-PLL) voltage-controlled oscillator (VCO) linear time-variant (LTV) mode given phase margin (PM)

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Arithmetic Progression Switched-Capacitor DC-DC Converter Topology With Soft VCR Transitions and Quasi-Symmetric Two-Phase Charge Delivery

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IEEE JOURNAL OF SOLID-state CIRCUITS 2022年第10期57卷 2919-2933页

作者： Jiang, Yang Law, Man-Kay Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI IME & FST ECE Macau Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This article presents an arithmetic progression (AP) switched-capacitor (SC) dc-dc converter topology for systematic step-down reconfigurable rational voltage conversion ratio (VCR) generation while exhibiting soft VCR transitions and quasi-symmetric two-phase charge delivery. The proposed AP topology features fixed steady-state voltage in all the flying capacitors ( $C_{{FLY}})$ irrespective of VCR change, essentially eliminating the internal $C_{{FLY}}$ hard-charging loss due to voltage rebalancing, effectively, improving the overall dynamic efficiency. It also achieves optimal steady-state slow-/fast-switching loss. Furthermore, due to the inherent quasi-symmetric output charge ( $Q_{{OUT}})$ delivery property in the two-phase switching operations, the proposed topology alleviates the VCR-dependent imbalanced per-phase $Q_{{OUT}}$ delivery to relax the $C_{{OUT}}$ requirement in a single-branch converter implementation. We propose a cross-coupled bootstrapping driver (XCBD) operated at half of the converter switching frequency ( $f_{{SW}})$ to adaptively control the flying power switches without relying on dual-branch interleaved architecture. Fabricated in 65-nm CMOS, the implemented AP chip prototype achieves a step-down VCR of 5:4/3/2/1 and converts a 1.5-V input to a 0.18-1.19-V output. With a measured steady-state peak power conversion efficiency (PCE) of 93.7%, this work can deliver a maximum output current of 400 mA while attaining an average conversion efficiency of up to 89% under a periodic VCR transition at 100 kHz as benefitted from the intrinsic soft VCR transition and low conduction loss properties.

关键词： Video recording Topology Steady-state Voltage Capacitors Switches Voltage control Bootstrapping driver charge sharing dc-dc converter reconfigurable soft transition switched-capacitor (SC) topology voltage conversion ratio (VCR)

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An Isolated DC-DC Converter With Full-Duplex Communication Using a Single Pair of Transformers

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IEEE JOURNAL OF SOLID-state CIRCUITS 2025年第3期60卷 1070-1081页

作者： Hu, Tingxu Lu, Yan Martins, Rui P. Huang, Mo Univ Macau Fac Sci & Technol FST State Key Lab Analog & Mixed Signal VLSI Dept Elect & Comp Engn ECEInst Microelect Macau 999078 Peoples R China Univ Macau Inst Microelect Macau 999078 Peoples R China

This article presents a 200-MHz isolated dc-dc converter for simultaneous power and full-duplex data transfer using a single pair of transformers, for the applications of low-cost galvanic isolation. The converter operates at high frequencies using a self-oscillating topology and implements a full-duplex 4-frequency-shift keying (FSK) communication through primary-side capacitance modulation and secondary-side 1X/2X rectification. We propose an adaptive bias circuit to address the sub-harmonic oscillation issue and to minimize the power MOSFET on-resistance. The primary and secondary-side chips are fabricated in 0.18-mu m bipolar-CMOS-DMOS (BCD) process with a 12.9-mm(2) PCB transformer pair. The overall circuit achieves a 37% peak efficiency with a maximum output power of 750 mW. It transfers 54-/18-Mb/s full-duplex data with a bit error rate (BER) below 10 (-6) .

关键词： Rectifiers Oscillators Modulation Frequency shift keying Full-duplex system Switches Logic gates Digital isolator frequency-shift keying (FSK) isolated power converter power oscillator

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A High-Performance Dual-Topology CMOS Rectifier With 19.5-dB Power Dynamic Range for RF-Based Hybrid Energy Harvesting

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (vlsi) SYSTEMS 2023年第8期31卷 1253-1257页

作者： Choo, Alexander Ramiah, Harikrishnan Churchill, Kishore Kumar Pakkirisami Chen, Yong Mekhilef, Saad Mak, Pui-In Martins, Rui P. Univ Malaya Fac Engn Dept Elect Engn Kuala Lumpur 50603 Malaysia Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME ECE FST Macau Peoples R China

This brief reports a dual-topology CMOS rectifier with an extended power dynamic range (PDR) for radio frequency (RF)-based hybrid energy harvesting (RF-HEH) systems. By leveraging both the cross-coupled differential drive (CCDD) and the Dickson topologies with high forward conduction and low reverse leakage, we obtain an extension of the rectifier's PDR by adaptively disabling the CCDD counterpart and enabling the Dickson counterpart to dominate the rectifier's performance during high-power operation. Apart from that, we formulate a rectifier-performance index (RPI), which accounts for the power conversion efficiency (PCE), the PDR, the sensitivity, and the load resistance of the rectifier to provide an adequate performance benchmark with the state-of-the-art rectifiers. Fabricated in a 130-nm CMOS, the proposed dual-topology rectifier measures a wide PDR of 19.5 dB with a peak PCE of 78.4% for a 100-kO load operating at 900 MHz. Besides, our prototype records the highest RPI of 19.2 compared to the recent arts operating at GSM900.

关键词： Rectifiers Radio frequency Sensitivity Topology Threshold voltage Very large scale integration Energy harvesting Power conversion efficiency (PCE) power dynamic range (PDR) radio frequency (RF)-based hybrid energy harvesting (RF-HEH)

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An Emulated Curve Assisted Fast-Transient Buck Converter With One-Cycle Charge Balance

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IEEE JOURNAL OF SOLID-state CIRCUITS 2025年

作者： Tang, Zihao Lu, Yan Martins, Rui P. Huang, Mo Univ Macau Fac Sci & Technol FST Dept Elect & Comp Engn ECE Inst MicroelectState Key Lab Analog & Mixed Signa Macau Peoples R China Univ Macau Inst Microelect Macau Peoples R China Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI ECEFST Macau Peoples R China

This article proposes an emulated peak/valley curve-assisted fast-transient buck converter that achieves almost one-cycle charge balance (OCB) load transient response. The previous OCB works require three-parameter calibration to mimic the output capacitor's RLC, and high-speed inductor current sensor. Comparatively, this work fulfills a one-parameter calibration with reduced design complexity. Additionally, we employ a modified double adaptive bound (DAB) hysteretic control to enhance both transient detection speed and output voltage regulation. The prototype chip fabricated in a 180-nm BCD process, exhibits a measured maximum deviation-from-ideal (DFI) rate of 5.5% for output voltage undershoot/overshoot (US/OS) and recovery time under different load-step conditions. This implies that the transient performance is close to the theoretical optimum with the proposed OCB scheme. The measured load regulation is improved to 0.05%/A by the modified DAB scheme.

关键词： Transient analysis Buck converters Accuracy Sensors Inductors Calibration Transient response Delays Voltage Switches Buck converter calibration double adaptive boundary hysteretic control fast transient one-cycle charge balance (OCB)

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A 5.99-GHz VCO With Wideband-Differential-Mode Second Harmonic Resonance Achieving-138.9 dBc/Hz Phase Noise at an Offset of 10 MHz

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IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS 2024年第11期34卷 1267-1270页

作者： Yang, Chaowei Chen, Yong Huang, Yunbo Martins, Rui P. Mak, Pui-In Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME ECE FST Macau Peoples R China Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This article presents a voltage-controlled oscillator (VCO) with wideband-differential-mode (DM) second harmonic resonance. It features a single-turn multitap inductor plus a small tail resonator to boost the drain-to-gate voltage gain (AV). It also creates intrinsic-high-Q impedance peaks at the fundamental and double oscillation frequencies, which simultaneously achieves phase noise (PN) and 1/f(3 )PN-corner reduction. Prototyped in 65-nm CMOS, the 5.99-GHz VCO scores a -138.9 dBc/Hz PN at an offset of 10 MHz and consumes 3.17 mW of power with a 0.67 V supply. The achieved figure-of-merit (FoM) values were 177.5, 186.6, and 189.4 dBc/Hz at an offset of 0.1, 1, and 10 MHz, with a 1/f(3) PN corner of 400 kHz. Over a 14% tuning range (TR), without any additional harmonic tuning, the VCO upholds a consistent FoM > 189 dBc/Hz at an offset of 10 MHz. The core area is 0.465 mm(2).

关键词： 1/ f (3 )pn corner CMOS figure-of-merit (FoM) figure-of-merit (FoM) impulse sensitivity function (ISF) impulse sensitivity function (ISF) phase noise (PN) phase noise (PN) voltage-controlled oscillator (VCO) voltage-controlled oscillator (VCO) wideband-harmonic shaping wideband-harmonic shaping wideband-harmonic shaping

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A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter,-258.7-dB FOM, and-75.17-dBc Reference Spur

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (vlsi) SYSTEMS 2023年第2期31卷 188-198页

作者： Huang, Yunbo Chen, Yong Zhao, Bo Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME ECE FST Macau Peoples R China Zhejiang Univ Inst VLSI Design Hangzhou 310027 Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This article presents a low-jitter and low-spur type-II sampling phase-locked loop (S-PLL). The innovative introduction of a differential parallel-series double-edge sampling phase detector (S-PD) achieves a high phase-detection gain and reduces the S-PLL in-band phase noise (PN). Incorporating a transformer-based harmonic-rich shaping voltage-controlled oscillator (VCO), the proposed S-PLL prototyped in a 65-nm CMOS, operates at 3.6 GHz and scores an integrated jitter of 43.1 fsrms integrated from 1 kHz to 100 MHz, it also exhibits a jitter-power figure-of-merit (FOM) of -258.7 dB. The measured reference (REF) spur is -80.34 dBc at f(REF) and -75.17 dBc at 2 f(REF), respectively.

关键词： Phase locked loops Voltage-controlled oscillators Jitter Very large scale integration Topology Clocks Capacitors CMOS figure-of-merit (FOM) harmonic-rich voltage-controlled oscillator (VCO) integrated jitter phase-detection gain (KPD) reference (REF) feedthrough suppression sampling phase-locked loop (S-PLL) type-I type-II

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