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An 840-to-970 MHz Multimodal Wake-Up Receiver With a Q -Equalized Antenna-ED Interface and 2-Dimensional Wake-Up Identification

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第3期72卷 1165-1177页

作者： Yang, Zhizhan Zhang, Haochen Yin, Jun Martins, Rui P. Mak, Pui-In Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Dept ECEFac Sci & Technol Macau Peoples R China

The article introduces an antenna-envelope detector (ED) co-designed wake-up receiver (WuRX) that can automatically detect the frequency-hopping sequence from 840 to 970 MHz. Prototyped in 65nm CMOS, the WuRX supports three modes: 1) low-power mode that achieves - 68 dBm sensitivity with 9.9nW power consumption, 2) Q-enhanced mode that provides 22 dB rejection to an on-off-keying (OOK) modulated pseudo-random-bit-sequence blocker at 10 MHz offset and 41 dB rejection to a continuous-wave one at 10 MHz offset, with a power consumption of 39.6 mu W and 3) 2-stage wake-up mode that combines the advantages of both the low- power mode and Q-enhanced mode, with a power consumption of 33.7 nW. These characteristics are achieved by exploiting 1) an antenna-ED interface where the Q-factor of the antenna is equal to the Q-factor of the capacitor to ensure a conjugate matching condition for the maximum available power transfer from the antenna to the ED, 2) a frequency tuner connected to the antenna-ED interface calibrated by a frequency-locked loop, and 3) a Q-booster reconfigured from the frequency tuner for boosting the passive gain and narrowing the bandwidth of the interface.

关键词： Antennas Resonant frequency Sensitivity Tuners Power demand Receiving antennas Radiofrequency identification Internet of Things (IoT) frequency-hopping loop antenna radio-frequency identification (RFID) envelope detector wake-up receiver ultra-low power Q-enhanced

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A 28-nm 3.32-nJ/Frame Compute-in-Memory CNN Processor With Layer Fusion for Always-on Applications

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Zhao, Yuanzhe He, Pengyu Zhu, Yan Martins, Rui P. Chan, Chi-Hang Zhang, Minglei Univ Macau Fac Sci & Technol Dept Elect & Comp Engn State Key Lab Analog & Mixed Signal VLSIInst Micr Macau Peoples R China

This work presents an always-on CNN processor featuring compute-in-memory (CIM) and layer-fusion (LF) techniques. It demonstrates an end-to-end neural network (NN) inference while eliminating memory accesses for both the weight and inter-layer activation, thus significantly saving associated energy. The analog LF-CIM processor combines charge-and time-domain multiply-accumulate (MAC) arrays in a fusional manner, avoiding the need for the interfacial analog-to-digital and digital-to-analog converters;it also supports a highly sparsity-adaptive network and exhibits low-voltage-supplied tolerance to circuit noise and variations, which facilitates an energy-efficient and robust CNN processor, simultaneously. Furthermore, the full-precision activation originating from the LF reduces the NN parameters and operations, while the inference accuracy is improved by the presented ensemble NN. The prototype processor is fabricated in a 28-nm CMOS process, demonstrating a fully on-chip MNIST inference with 97.9% accuracy. It operates at 3,508 frames per second while consuming 11.6 mu W at a 0.5-V supply;the achieved efficiency of 3.32 nJ/frame is over 50-fold than the state-of-the-art end-to-end MNIST accelerators.

关键词： Accuracy In-memory computing Engines Energy efficiency Convolutional neural networks Voltage System-on-chip Internet of Things Common Information Model (computing) Artificial intelligence Always-on processor CNN compute-in-memory (CIM) hybrid domain layer fusion sparsity-adaptive

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A VCF-Step-Reconfigurable Continuously Scalable-Conversion-Ratio Switched-Capacitor Converter

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IEEE JOURNAL OF SOLID-state CIRCUITS 2025年第2期60卷 626-637页

作者： Wang, Yuanfei Huang, Mo Chen, Qiujin Martins, Rui P. Lu, Yan Univ Macau Dept Elect & Comp Engn ECE State Key Lab Analog & Mixed Signal VLSI Fac Sci & Technol FSTInst Microelect Macau Peoples R China

This article proposes a V-CF -step-reconfigurable continuously scalable-conversion-reconfigurable CSC (RCSC). We first analyze the working principle of the conventional conversion-ratio SC (CSC) converter and why it has reduced efficiency over a wide voltage conversion ratio (VCR) range. Then, the proposed RCSC reconfigures and thus equalizes the step size of the flying capacitor C-F voltage (V-CF) according to the VCR. This maximizes efficiency over a wider range of VCRs, with limited circuitry complexity. Subsequently, we propose a gate control signal generation scheme that significantly reduces the cost overhead of the reconfiguration. The proposed RCSC can be used in either step-up or step-down mode and is compatible with maximum power point tracking (MPPT) in energy harvesting systems. Implemented with a 65-nm CMOS process, the proposed RCSC reaches a 90% peak efficiency using 34 V-CF steps and the widest normalized VCR range with > 75% efficiency.

关键词： Continuously scalable-conversion-ratio maximum power point tracking (MPPT) reconfigurable VCF step switched-capacitor (SC) converter wide voltage conversion ratio (VCR) range

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A 0.0019-mm² LC-Ring Oscillator With an Ultra-Compact Transformer Achieving 175.2 dBc/Hz FoM@1MHz and 202.4 dBc/Hz FoMA

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IEEE Transactions on Circuits and Systems II: Express Briefs 2025年第5期72卷 693-697页

作者： Zhao, Ya Huang, Lingao Wang, Runchen Yin, Jun Mak, Pui-In Geng, Li Fan, Chao Xi’an Jiaotong University School of Microelectronics Xi’an710049 China University of Macau State-Key Laboratory of Analog and Mixed-Signal VLSI Faculty of Science and Technology Department of ECE China

This brief describes an area-efficient LC-ring oscillator featuring an ultra-compact transformer resonator. The series inverters could be equivalent to the negative resistors providing gain compensation. The involved inverters and switched capacitor banks are fully integrated underneath the transformer resonator. Thus, with a comparable area of the typical ring oscillators, our oscillator shows significantly improved phase noise (PN) and figure-of-merit (FoM). Besides, we implemented the stacked coupling and distributed-coupling transformer-based LC-ring oscillators for the PN and FoM comparison. The stacked-coupling LC-ring oscillator can lower the PN with the same frequency and power budget. Fabricated in 40-nm CMOS, our stacked-coupling LC-ring oscillator scores a PN@1MHZ of -110.4 dBc/Hz across the frequency tuning range from 3.7 to 5.1 GHz with an active area of 0.0019 mm2, corresponding to a superior FoM (FoMA)@1MHz of 175.2 dBc/Hz (202.4 dBc/Hz) that is 4.2 dB (6 dB) higher than the distributed-coupling LC ring oscillator. © 2004-2012 IEEE.

关键词： Budget control

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A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM

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IEEE JOURNAL OF SOLID-state CIRCUITS 2025年第3期60卷 1103-1112页

作者： Tan, Fei Yu, Wei-Han Lin, Jinhai Un, Ka-Fai Martins, Rui P. Mak, Pui-In Univ Macau Inst Microelect Fac Sci & Technol ECE State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This article reports a keyword-spotting (KWS) chip with a significantly reduced false alarm rate (FAR) for voice-control edge devices. The key techniques are threefold: 1) transfer-computing speaker verification (SV)-assisted KWS that compresses the required parameters and enhances the KWS+SV computation efficiency while maintaining the KWS accuracy and reducing the overall FAR;2) hybrid-IF-domain computing that handles both the analog and digital input features (IFs), alleviating the tradeoff between the computation power and system accuracy of the first layer;and 3) scalable 5T-SRAM array that sustains the leakage and read power when it is upscaled. Benchmarking with the state-of-the-art, our SV-assisted KWS prototyped in 28-nm CMOS achieves the best-in-class energy efficiency of 1.73 nJ/decision, a decision latency of 2 ms, and a FAR of 1.8%. The achieved 12-class top-1 KWS accuracy is 91.8% for the Google speech command dataset (GSCD) and the core area is 0.121 mm(2) , including an 11-KB full SV-assisted KWS model. The described chip also shows the lowest-reported 12-class KWS power consumption of 1.73 mu W.

关键词： Computational modeling Accuracy Load modeling Vectors Task analysis Kernel Convolutional neural networks 5T-SRAMa convolutional neural network (CNN) input stationary keyword spotting (KWS) low-leakage memory speaker verification (SV) switched-capacitor circuits transfer-learning

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A 0.35-0.5-V 0.0136-mm² 12-MHz Digital Frequency-Locked Loop With 1.06%/V Line Sensitivity in 65-nm CMOS

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2025年第3期72卷 459-463页

作者： Shi, Dan Lei, Ka-Meng Martins, Rui P. Mak, Pui-In Univ Macau Inst Microelect Dept ECE State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Fac Sci & Technol Macau Peoples R China

This brief presents a fully integrated sub-0.5 V digital frequency-locked loop (DFLL) incorporating a clock-boosting RC network to secure frequency accuracy under ultra-low voltage (ULV) operation. It embodies 3 key features: 1) a clock-boosting RC network with a time constant tau = RC to set the nominal frequency, 2) a dynamic tail-boosted comparator with offset background calibration to facilitate operation in ULV regime, and 3) a hybrid digital-controlled oscillator (DCO) with resolution enhancement to uphold the frequency stability. Fabricated in 65-nm CMOS, the DFLL features a compact footprint of 0.0136 mm(2) and consumes 5.7 mu W under 0.35 V at room temperature. It achieves a line sensitivity of 1.06%/V across 0.35 to 0.5 V, and a frequency inaccuracy of 176 ppm/degrees C between -30 and 120 degrees C. Benefitting from the offset calibration technique to reduce the inband noise, the DFLL demonstrates outstanding jitter FoM(Jitter) of -224.5 dB and Allan deviation floor of <5 ppm, showcasing exceptional frequency stability.

关键词： Calibration Frequency locked loops Thermal stability Stability criteria Temperature measurement Switched mode power supplies Semiconductor device measurement Circuit stability Voltage Boosting RC oscillators digital frequency-locked loop (DFLL) Internet-of-Things (IoT) ultralow-voltage (ULV) low power energy harvesting

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Characterization and Modeling of MOSFET Series Resistance Down to 4 K

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IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY 2025年 13卷 297-302页

作者： Lin, Yuhuan Ma, Zhizhao Li, Shilong Wen, Tianyue Zhou, Yuxuan Su, Hao Zhou, Shenghua Lin, Longyang Li, Yida Chen, Kai Southern Univ Sci & Technol Sch Microelect Shenzhen 518055 Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI IME ECE FST Macau Macao Peoples R China

MOSFET parasitic series resistance (R-SD) is an important parameter when channel length scales down. This paper presents a systematic study of R-SD extracted from the mobility constant method down to 4 K. For the first time, the anomalous behavior of R-SD with temperature lowering is interpreted and modeled by combined effects of dopant freeze-out and mobility. Excellent fit between the standard N/P-MOSFET measurement data and this model for 40 nm bulk device from leading foundry is shown from 300 K to 4 K. In addition, R-SD change with width scaling combined with temperature effects is also discussed.

关键词： Resistance MOSFET circuits Logic gates MOSFET Semiconductor device modeling Junctions Electrical resistance measurement Cryogenics Conductivity Systematics Series resistance R-SD cryogenic extraction model

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A Series-LC-Assisted Oscillator Achieving-140.2 dBc/Hz Phase Noise and 187.5 dBc/Hz FoM at 10 MHz Offset From 10.7 GHz

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2025年第2期72卷 389-393页

作者： Zhan, Xiangxun Yin, Jun Martins, Rui P. Mak, Pui-In Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Fac Sci & Technol Dept Elect & Commun Engn Macau Peoples R China

This brief presents a series-LC-assisted oscillator. By utilizing the series LC, the tank impedance at the oscillation frequency is significantly reduced compared to the conventional parallel LC tank, which contributes to reducing the phase noise (PN). Additionally, large-size cross-coupled transistors should be utilized to maintain the oscillation due to the low tank impedance. This induces a large parasitic capacitance that limits the frequency tuning range (FTR) at high frequencies in the conventional cross-coupled oscillator. In contrast, the presented oscillator can operate above 10 GHz with a sufficient FTR, thanks to the capacitance-boosting capability of the series LC. Fabricated in a 65 nm CMOS process, the oscillator achieves a PN of -140.2 dBc/Hz at 10 MHz offset from a 10.7 GHz carrier, consuming a power consumption of 21 mW, resulting in a figure of merit (FoM) of 187.5 dBc/Hz.

关键词： Oscillators Impedance Resonant frequency Tuning Transistors Resonance Q-factor Parasitic capacitance Voltage Phase noise Phase noise (PN) figure of merit (FoM) series LC oscillator frequency tuning range (FTR)

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A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer

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IEEE JOURNAL OF SOLID-state CIRCUITS 2025年第2期60卷 443-455页

作者： Cao, Yuefeng Zhang, Minglei Zhu, Yan Martins, Rui P. Chan, Chi-Hang Univ Macau Fac Sci & Technol Dept Elect & Comp Engn State Key Lab Analog & Mixed Signal VLSI Macau 999078 Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

Ring amplifier (RingAmp)-based multiplying digital-to-analog converters (MDACs) feature high energy efficiency and linearity;however, their process, supply voltage, and temperature (PVT)-sensitive transient responses require significant timing overhead, limiting the speed of the pipelined analog-to-digital converters (ADCs). This work introduces a sturdy RingAmp (SRingAmp), which stabilizes the gain, gain-bandwidth product (GBW), phase margin (PM), and transient response by building up compensatory coordination, achieving significant speed and PVT-robustness advantages over prior RingAmps. Furthermore, a time-domain ADC is utilized as the sub-quantizer with two techniques, including a common-mode shifting (CMS) scheme and a partial power-down (PD) operation for the voltage-to-time converter (VTC) and the time-to-digital converter (TDC), respectively. The former allows a near mid-supply common-mode input without degrading the linearity, and the latter improves the power efficiency. With these techniques, a single-channel 12-bit pipelined ADC achieves 2 GS/s in 28-nm CMOS with measured 60.4-dB SNDR and 75.8-dB SFDR at a Nyquist input, consuming 27 mW from a 1.0-V supply and yielding a Schreier figure of merit (FoM) of 166.1 dB.

关键词： Voltage Gain Calibration Time-domain analysis Reviews High frequency Very large scale integration analog-to-digital converter (ADC) process supply voltage and temperature (PVT)-robust sturdy ring amplifier (SRingAmp) time-domain quantizer time-to-digital converter (TDC) voltage-to-time converter (VTC)

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IEEE Young Professionals in Circuits and Systems (YPCAS) Forum 2024 at University of Macau, Macau SAR, China

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IEEE CIRCUITS AND SYSTEMS MAGAZINE 2025年第1期25卷 88-92页

作者： Lam, Chi-Seng Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Fac Sci & Technol Dept Elect & Comp Engn Macau Peoples R China

IEEE Young Professionals in Circuits and Systems (YPCAS), under the IEEE Circuits and Systems Society (CASS) Diversity, Equity, and Inclusion Committee (DEI), successfully organized The IEEE Young Professionals in Circuits and Systems (YPCAS) Forum 2024 at the University of Macau, Macau SAR, China from November 27-28, 2024. This forum invited 7 young professors/ scholars from the field of circuits and systems to deliver different technical talks, introduce their career development, interact with young researchers and students to broaden their horizons, and provide guidance for their future career development. This forum was supported by the 2024 CASS Outreach Initiative, IEEE CASS DEI, The Science and Technology Development Fund, Macau SAR (FDCT), IEEE Macau Section, IEEE Macau Circuits and Systems Society (CAS) Chapter, and state key laboratory of analog and mixed-signal vlsi & Institute of Microelectronics of University of Macau.

关键词： Circuits and systems iEEE Young Professionals in Circuits and Systems (YPCAS) Forum 2024

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