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Bioinspired Camouflage Fibers with computer Vision-Guided Chromatic Adaptation

ACS Nano 2025年 2025 May 16页

作者： Huang, Luyao Cheng, Tingyu Zhang, Xianzhe Zhang, Haichao Deshpande, Tejonidhi Li, Yuanqiao Xu, Zhi Abowd, Gregory D. Fu, Yun Liu, Yongmin Hester, Josiah Li, Jun Zhu, Hongli Department of Mechanical and Industrial Engineering Northeastern University Boston 02115 MA United States College of Computing Georgia Institute of Technology Atlanta 30332 GA United States Department of Electrical and Computer Engineering Northeastern University Georgia Institute of Technology Boston 02115 MA United States Khoury College of Computer Sciences Northeastern University Boston 02115 MA United States State Key Laboratory of Advanced Papermaking and Paper-based Materials South China University of Technology Guangzhou 510640 China

The development of intelligent camouflage systems demands advanced materials and control strategies for dynamic environmental adaptation. Here, we demonstrate a bioinspired camouflage system using hydroxypropyl cellulose (HPC), a cellulose derivative that forms cholesteric liquid crystals with mechanically tunable structural colors. By integrating HPC fibers with computer vision-assisted control, we achieve autonomous color matching with the environment through precise mechanical manipulation. Our system employs computer vision and a custom-designed wavelength-value (WV) mapping algorithm to analyze surroundings and control fiber tension, enabling direct modulation of the reflected wavelength. The closed-loop control system achieves color matching with less than 5% error at room temperature and maintains over 95% accuracy across temperatures from 15 to 35 °C. The HPC fibers exhibit reversible color transitions spanning the visible spectrum (400-700 nm). This integration of sustainable biomaterials with computer vision-guided mechanical control demonstrates an alternative approach for advanced camouflage applications, including military concealment and anticounterfeiting technologies. © 2025 American Chemical Society.

关键词： artificial intelligence chromatic adaptation computer vision hydroxypropyl cellulose structural colors

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Statistical Interconnect Crosstalk Noise Model and Analysis for Process Variations

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Chinese Journal of Electronics 2015年第1期24卷 83-87页

作者： LI Jianwei DONG Gang WANG Zeng YE Xiaochun Faculty of Automation and Information Engineering Xi'an University of Technology State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Microelectronics Institute Xidian University College of Physics Sicence Qingdao University

When operating frequency is over several gigahertz, the effect of inductance plays an important role and should be included for accurate and speed crosstalk noise analysis. And for new generation IC(Integrated circuit) design tools, the crosstalk noise analysis tools should consider the influence of process variations. In this paper, we propose coupled RLC crosstalk noise distributed parameter model with capacitive load termination. And we develop the framework that how to use the crosstalk noise model for process variations. Our results show that compare with HSPICE, the critical data errors of proposed model are within 1% and the relative errors occurred between calculated values for process variations and HSPICE Monte Carlo simulation values are less than 5%. The key features of the new model include:(1) The impact of inductance on crosstalk noise is considered;(2) The model can be used for process variations analysis;(3) The model reflect the effects of load capacitance directly;(4) The numerical inversion of Laplace transform is introduced for improving speed. So the proposed model meets the needs of future IC design both in speed and accuracy.

关键词： Crosstalk noise Interconnect Inductance Process variation Statistical

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KANsformer for Scalable Beamforming

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IEEE Transactions on Vehicular technology 2025年

作者： Xie, Xinke Lu, Yang Chi, Chong-Yung Chen, Wei Ai, Bo Niyato, Dusit Beijing Jiaotong University State Key Laboratory of Advanced Rail Autonomous Operation Beijing100044 China Beijing Jiaotong University School of Computer Science and Technology Beijing100044 China National Tsing Hua University Institute of Communications Engineering Department of Electrical Engineering Hsinchu30013 Taiwan Beijing Jiaotong University School of Electronics and Information Engineering Beijing100044 China Nanyang Technological University College of Computing and Data Science 639798 Singapore

This paper proposes an unsupervised deep-learning (DL) approach by integrating Transformer and Kolmogorov-Arnold networks (KAN) termed KANsformer to realize scalable beamforming for mobile communication systems. Specifically, we consider a classic multi-input single-output energy efficiency maximization problem subject to the total power budget. The proposed KANsformer first extracts hidden features via a multi-head self-attention mechanism and then reads out the desired beamforming design via KAN. Numerical results are provided to evaluate the KANsformer in terms of generalization performance, transfer learning and ablation experiment. Overall, the KANsformer outperforms the existing benchmark DL approaches, and is adaptable to the variation in the number of mobile users with real-time and near-optimal inference. © 1967-2012 IEEE.

关键词： Budget control

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IMPULP:A Hardware Approach for In-Process Memory Protection via User-Level Partitioning

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Journal of computer Science & technology 2020年第2期35卷 418-432页

作者： Yang-Yang Zhao Ming-Yu Chen Yu-Hang Liu Zong-Hao Yang Xiao-Jing Zhu Zong-Hui Hong Yun-Ge Guo State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China Peng Cheng Laboratory Shenzhen 518055China

In recent years many security attacks occur when malicious codes abuse in-process memory *** to the increasing complexity,an application program may call third-party code which cannot be controlled by programmers but may contain security *** a result,the users have the risk of suffering information leakage and control flow ***,current solutions like Intel memory protection extensions(MPX)severely degrade performance,while other approaches like Intel memory protection keys(MPK)lack flexibility in dividing security *** this paper,we propose IMPULP,an effective and efficient hardware approach for in-process memory *** rationale of IMPULP is user-level partitioning that user code segments are divided into different security domains according to their instruction addresses,and accessible memory spaces are specified dynamically for each domain via a set of boundary *** instruction related to memory access will be checked according to its security domain and the corresponding boundaries,and illegal in-process memory access of untrusted code segments will be *** can be leveraged to prevent a wide range of in-process memory abuse attacks,such as buffer overflows and memory *** verification,an FPGA prototype based on RISC-V instruction set architecture has been *** present eight tests to verify the effectiveness of IMPULP,including five memory protection function tests,a test to defense typical buffer overflow,a test to defense famous memory leakage attack named Heartbleed,and a test for security *** execute the SPEC CPU2006 benchmark programs to evaluate the efficiency of *** performance overhead of IMPULP is less than 0.2%runtime on average,which is ***,the resource overhead is less than 5.5%for hardware modification of IMPULP.

关键词： in-process isolation memory protection out-of-bounds user-level partitioning

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Efficient Algorithm for Energy-Aware Virtual Network Embedding

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Tsinghua Science and technology 2016年第4期21卷 407-414页

作者： Shuxian Jia Guiyuan Jiang Peilan He Jigang Wu School of Computer Software Technology Zhejiang University Ningbo 315048 China School of Computer Science and Engineering Nanyang Technological University 639798 Singapore State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Network virtualization is a promising approach for resource management that allows customized Virtual Networks （VNs） to be multiplexed on a shared physical infrastructure. A key function that network virtualization can provide is Virtual Network Embedding （VNE）, which maps virtual networks requested by users to a shared substrate network maintained by an Internet service provider. Existing research has worked on this, but has primarily focused on maximizing the revenue of the Internet service provider. In this paper, we consider energy-aware virtual network embedding, which aims at minimizing the energy consumption for embedding virtual networks in a substrate network. In our optimization model, we consider energy consumption of both links and nodes. We propose an efficient heuristic to assign virtual nodes to appropriate substrate nodes based on priority, where existing activated nodes have higher priority for hosting newly arrived virtual nodes. In addition, our proposed algorithm can take advantage of activated links for embedding virtual links so as to minimize total energy consumption. The simulation results show that, for all the cases considered, our algorithm can improve upon previous work by an average of 12.6% on acceptance rate, while the consumed energy can be reduced by 12.34% on average.

关键词： virtualization technology virtual network embedding energy efficient optimization algorithm

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CNN Feature Boosted SeqSLAM for Real-Time Loop Closure Detection

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Chinese Journal of Electronics 2018年第3期27卷 488-499页

作者： BAI Dongdong WANG Chaoqun ZHANG Bo YI Xiaodong YANG Xuejun College of Computer National University of Defense Technology State Key Laboratory of High Performance Computing National University of Defense Technology National Institute of Defense Technology Innovation

This paper proposes an efficient and robust Loop closure detection(LCD) method based on Convolutional neural network(CNN) feature. The primary method is called SeqCNNSLAM, in which both the outputs of the intermediate layer of a pre-trained CNN and the outputs of traditional sequence-based matching procedure are incorporated, making it possible to handle the viewpoint and condition variance properly. An acceleration algorithm for SeqCNNSLAM is developed to reduce the search range for the current image, resulting in a new LCD method called A-SeqCNNSLAM. To improve the applicability of A-SeqCNNSLAM to new environments, O-SeqCNNSLAM is proposed for online parameters adjustment in A-SeqCNNSLAM. In addition to the above work, we further put forward a promising idea to enhance Seq SLAM by integrating the both CNN features and VLAD's advantages called patch based Seq CNNSLAM(P-SeqCNNSLAM), and provide some preliminary experimental results to reveal its performance.

关键词： Simultaneous localization and mapping(SLAM) Loop closure detection(LCD) Convolutional neural network(CNN) SeqSLAM SeqCNNSLAM A-SeqCNNSLAM O-SeqCNNSLAM P-SeqCNNSLAM

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Improving DNN Accuracy on MLC PIM via Black-box Fine-tuning

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IEEE Transactions on computer-Aided Design of Integrated Circuits and Systems 2024年第6期44卷 2277-2286页

作者： Lv, Hao Zhang, Lei Wang, Ying Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences Beijing100089 China The State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100089 China

Resistive random access memory (RRAM) emerges as a promising technology for developing energy-efficient deep neural network (DNN) accelerators, owing to its analog computing paradigm for matrix-vector multiplication. However, the inherent non-ideal device features of RRAM cells, such as device variation, read disturbances, and limited on/off ratio, present challenges for model deployment. Therefore, to ensure accurate storage and computing precision for RRAM-based accelerators, a widely used practice is encoding a DNN weight by multiple cells, resulting in significant memory overhead and underutilization. This challenge is further exacerbated by the rapid increases in model size witnessed in recent years. While the one-to-one weight-cell mapping strategy can improve memory utilization, it inevitably introduces deviations in the mapped DNN weight from the desired value due to RRAM variation issues, leading to model accuracy degradation. In response to this challenge, we abstract the model optimization on RRAM chips as a black-box optimization problem, aimed at optimizing model accuracy without the requirement of precise weight programming. We systematically analyze the model optimization behavior on multi-level RRAM devices by investigating the accuracy recovery process of various fine-tuning strategies in recovering model performance under the black-box setting. Based on the analysis, we propose a black-box finetune scheme to recover the model performance for multilevel RRAM under the black-box setting. Our proposed scheme leverages knowledge distillation and exploits input/output information of the model on RRAM to guide the fine-tuning process, finally restoring its accuracy. Experimental results demonstrate the efficacy of our black-box fine-tuning scheme, achieving nearly complete recovery of model performance. Our approach yields over a 3% improvement in model accuracy compared to variation-aware training approaches. © 1982-2012 IEEE.

关键词： Energy efficiency

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A Non-Stop Double Buffering Mechanism for Dataflow architecture

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Journal of computer Science & technology 2018年第1期33卷 145-157页

作者： Xu Tan Xiao-Wei Shen Xiao-Chun Ye Da Wang Dong-Rui Fan Lunkai Zhang Wen-Ming Li Zhi-Min Zhang Zhi-Min Tang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing 100049 China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi 214125 China Department of Computer Science The University of Chicago Chicago IL 60637 U.S.A.

Double buffering is an effective mechanism to hide the latency of data transfers between on-chip and off-chip memory. However, in dataflow architecture, the swapping of two buffers during the execution of many tiles decreases the performance because of repetitive filling and draining of the dataflow accelerator. In this work, we propose a non-stop double buffering mechanism for dataflow architecture. The proposed non-stop mechanism assigns tiles to the processing element array without stopping the execution of processing elements through optimizing control logic in dataflow architecture. Moreover, we propose a work-flow program to cooperate with the non-stop double buffering mechanism. After optimizations both on control logic and on work-flow program, the filling and draining of the array needs to be done only once across the execution of all tiles belonging to the same dataflow graph. Experimental results show that the proposed double buffering mechanism for dataftow architecture achieves a 16.2% average efficiency improvement over that without the optimization.

关键词： non-stop double buffering dataflow architecture high-performance computing

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Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platforms

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Journal of computer Science & technology 2014年第1期29卷 21-37页

作者：吕方崔慧敏王蕾刘磊武成岗冯晓兵游本中 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences CCF ACM IEEE Department of Computer Science and Engineering University of Minnesota at Twin Cities Institute of Information Science Academia Sinica

Efficiency of batch processing is becoming increasingly important for many modern commercial service centers, e.g., clusters and cloud computing datacenters. However, periodical resource contentions have become the major performance obstacles for concurrently running applications on mainstream CMP servers. I/O contention is such a kind of obstacle, which may impede both the co-running performance of batch jobs and the system throughput seriously. In this paper, a dynamic I/O-aware scheduling algorithm is proposed to lower the impacts of I/O contention and to enhance the co-running performance in batch processing. We set up our environment on an 8-socket, 64-core server in Dawning Linux Cluster. Fifteen workloads ranging from 8 jobs to 256 jobs are evaluated. Our experimental results show significant improvements on the throughputs of the workloads, which range from 7% to 431%. Meanwhile, noticeable improvements on the slowdown of workloads and the average runtime for each job can be achieved. These results show that a well-tuned dynamic I/O-aware scheduler is beneficial for batch-mode services. It can also enhance the resource utilization via throughput improvement on modern service platforms.

关键词： chip multiprocessor batch processing co-running I/0 contention scheduling

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Helix Scan:A Scan Design for Diagnosis

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Tsinghua Science and technology 2007年第S1期12卷 83-88页

作者：王飞胡瑜李晓维 Graduate School of Chinese Academy of Sciences Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

Scan design is a widely used design-for-testability technique to improve test quality and efficiency. For the scan-designed circuit, test and diagnosis of the scan chain and the circuit is an important process for silicon debug and yield learning. However, conventional scan designs and diagnosis methods abort the subsequent diagnosis process after diagnosing the scan chain if the scan chain is faulty. In this work, we propose a design-for-diagnosis scan strategy called helix scan and a diagnosis algorithm to address this issue. Unlike previous proposed methods, helix scan has the capability to carry on the diagnosis process without losing information when the scan chain is faulty. What is more, it simplifies scan chain diagnosis and achieves high diagnostic resolution as well as accuracy. Experimental results demonstrate the effectiveness of our design.

关键词： test diagnosis scan chain diagnosis design for diagnosis (DFD)

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