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检索条件"机构=State Key Laboratory of Computer Architecture~ Institute of Computing Technology"

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BTMD: A framework of binary translation based malcode detector

BTMD: A framework of binary translation based malcode detect...

引用

4th International Conference on Cyber-Enabled Distributed computing and Knowledge Discovery, CyberC 2012

作者： Shan, Zheng Guo, Haoran Pang, Jianmin Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China National Digital Switching System Engineering and Technology Research Center Zhengzhou China

ISBN: (纸本)9780769548104

Binary Translation technology is used to convert binary code of one Instruction Set architecture (ISA) into another. This technology can solve the software-inheritance problem and ISA-compatibility between different computers architecture. In this paper, we describe BTMD (Binary Translation based Malcode Detector), a novel framework that exploits static and dynamic binary translation features to detect broad spectrum malware and prevent its execution. By operating directly on binary code with MD Rules on the availability of source code, BTMD is appropriate for translating low-level binary code to high-level proper representation, obtaining CFG (Control Flow Graph) and other high-level Control Structure by MD Parser. Then Critical API Graph based on CFG is generated to do sub graph matching with the defined Malware Behavior Template. MD Engine in BTMD is called to undertake the process to take on the remaining code analysis. Compared with other detection approaches, BTMD is found to be very efficient in terms of detection capability and false alarm rate. © 2012 IEEE.

关键词： Binary codes

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Extendable pattern-oriented optimization directives

Extendable pattern-oriented optimization directives

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作者： Cui, Huimin Xue, Jingling Wang, Lei Yang, Yang Feng, Xiaobing Fan, Dongrui Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Beijing China School of Computer Science and Engineering University of New South Wales Sydney NSW Australia

Algorithm-specific, that is, semantic-specific optimizations have been observed to bring significant performance gains, especially for a diverse set of multi/many-core architectures. However, current programming models and compiler technologies for the state-of-the-art architectures do not exploit well these performance opportunities. In this article, we propose a pattern-making methodology that enables algorithm-specific optimizations to be encapsulated into "optimization patterns". Such optimization patterns are expressed in terms of preprocessor directives so that simple annotations can result in significant performance improvements. To validate this new methodology, a framework, named EPOD, is developed to map these directives into the underlying optimization schemes for a particular architecture. It is difficult to create an exact performance model to determine an optimal or near-optimal optimization scheme (including which optimizations to apply and in which order) for a specific application, due to the complexity of applications and architectures. However, it is trackable to build individual optimization components and let compiler developers synthesize an optimization scheme from these components. Therefore, our EPOD framework provides an Optimization Programming Interface (OPI) for compiler developers to define new optimization schemes. Thus, new patterns can be integrated into EPOD in a flexible manner. We have identified and implemented a number of optimization patterns for three representative computer platforms. Our experimental results show that a pattern-guided compiler can outperform the state-of-theart compilers and even achieve performance as competitive as hand-tuned code. Therefore, such a patternmaking methodology represents an encouraging direction for domain experts' experience and knowledge to be integrated into general-purpose compilers. © 2012 ACM.

关键词： Semantics

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Energy-efficient network routing with discrete cost functions

Energy-efficient network routing with discrete cost function...

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9th Annual Conference on Theory and Applications of Models of Computation, TAMC 2012

作者： Wang, Lin Fernández Anta, Antonio Zhang, Fa Hou, Chenying Liu, Zhiyong Key Lab. of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences China Institute IMDEA Networks Spain China State Key Lab. for Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate University of Chinese Academy of Sciences China

ISBN: (纸本)9783642299513

Energy consumption is an important issue in the design and use of networks. In this paper, we explore energy savings in networks via a rate adaptation model. This model can be represented by a cost-minimization network routing problem with discrete cost functions. We formulate this problem as an integer program, which is proved to be NP-hard. Then a constant approximation algorithm is developed. In our proposed method, we first transform the program into a continuous-cost network routing problem, and then we approximate the optimal solution by a two-step rounding process. We show by analysis that, for uniform demands, our method provides a constant approximation for the uniform network routing problem with discrete costs. A bicriteria network routing problem is also developed so that a trade-off can be made between energy consumption and network delay. Analytical results for this latter model are also presented. © 2012 Springer-Verlag.

关键词： Network routing

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A compiler-assisted runtime-prefetching scheme for heterogeneous platforms

引用

8th International Workshop on OpenMP, IWOMP 2012

作者： Chen, Li Shou, Baojiang Hou, Xionghui Huang, Lei State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences No.6 Kexueyuan South Road Beijing 100190 China Department of Computer Science Prairie View A and M University Prairie View TX 77446 United States

ISBN: (纸本)9783642309601

GPGPU has been widely used in recent years in both academia and industry. Many research for benchmarks on GPUs were reported to achieve over 100 times speedup, however, due to the high overhead of data transfer between GPU and CPU in real-world applications, the achievements are dramatically limited. In the case of using multiple GPUs, the situation is even worse. Another difficulty raised by the GPGPUs is the programming productivity. In this work, we introduce a new language extension to the easy-to-use programming model OpenMP, implement a runtime and a prefetching mechanism to further extend our work in support of OpenMP on heterogeneous platforms. The new language extension allows the OpenUH compiler to generate efficient code for heterogeneous platforms with multiple GPUs included. To improve the performance of applications with lots of data transfer, we implement runtime inter-thread dataflow analysis and a runtime-prefetching mechanism with the help of compiler analysis, making the data transfer overlap with the computation as much as possible. We have evaluated our prefetching system using benchmarks including NPB SP, kmeans and nbody. In these experiments, we achieve speedups of 1.23, 1.4 and 1.32 respectively compared with the versions without prefetching support. © 2012 Springer-Verlag.

关键词： Data transfer

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Libvmi: A Library for Bridging the Semantic Gap between Guest OS and VMM

Libvmi: A Library for Bridging the Semantic Gap between Gues...

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International Conference on computer and Information technology (CIT)

作者： Haiquan Xiong Zhiyong Liu Weizhi Xu Shuai Jiao State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Semantic gap is one of the most important problems in the virtualized computer systems. Solving this problem not only helps to develop security and virtual machine monitoring applications, but also benefits for VMM resource management and VMM-based service implementation. In this paper, we first review the general architecture of virtual computer systems, especially the interaction principles between Guest OS and VMM so as to better understand the causes of semantic gap. Then we consider how to build a library that can integrate the commonalities existing in different VMMs and Guest OSes. It should be general enough to facilitate the above mentioned applications development. In order to more clearly illustrate this issue, we select Libvmi as the case study, elaborating its design philosophy and implementation. Finally, we describe how to use Libvmi with two application examples and verify its correctness and effectiveness.

关键词： Libraries Virtual machining Semantics Virtual machine monitors computer architecture Hardware computers

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SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write

SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase C...

引用

Asian Test Symposium (ATS)

作者： Yuntan Fang Huawei Li Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Modern video applications such as video codecs are memory-intensive. As an emerging non-volatile memory technology, phase change memory (PCM) will benefit video applications due to its high density, low leakage power and superior scalability. However, PCM consumes high write energy and can only sustain a limited write number. Hence it is necessary to reduce the write number of PCM for video applications. In this paper, we propose SoftPCM to enhance both energy efficiency and lifetime of PCM. SoftPCM utilizes the error tolerance characteristic of video applications to relax the accuracy of write operations. Experimental results show that SoftPCM can reduce 22% writes and thus improve energy efficiency and lifetime of PCM with slight video quality degradation.

关键词： Phase change materials Video recording Quality assessment Random access memory Hardware Approximation methods Reflective binary codes

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Statistical SDFC: A metric for evaluating test quality of small delay faults

Statistical SDFC: A metric for evaluating test quality of sm...

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International Symposium on VLSI Design, Automation and Test

作者： Xuefeng Zhu Huawei Li Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781457720802

As the technology node continues to shrink, an effective and accurate metric is essential to measure the test quality of small delay faults (SDFs), which may cause failure at circuit outputs. Owing to including gross delay fault (GDF) coverage, prior metrics cannot concentrate on the detection of SDFs. We propose a new metric, statistical SDF Coverage (S-SDFC), for differentiating SDFs and GDFs and evaluating the test quality of SDFs under the statistical delay quality model. Experimental results show that S-SDFC is more conservative and effective in evaluating the quality of test sets in detecting SDFs and outperforms other metrics in guiding test generation.

关键词： Circuit faults Delay Automatic test pattern generation Clocks Integrated circuit modeling

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A testability-aware low power architecture

A testability-aware low power architecture

引用

25th IEEE International System-on-Chip Conference, SOCC 2012

作者： Wang, Gang Wang, Jian Qi, Zi-Chu Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Loongson Technology Corporation Limited Beijing 100190 China

ISBN: (纸本)9781467312950

Test power consumption is becoming a major concern in low power integrated circuits(ICs). This paper presents a revised low power compression architecture for scan test. In this paper, the variance in power consumption is used to select test pattern during scan test, and a low power feedback MUX is added to the scan chains. Simulation results by mathematical methods show that the proposed test architecture is promising in reduction of power consumption. © 2012 IEEE.

关键词： Electric power utilization

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Cache locking for network processing acceleration

Cache locking for network processing acceleration

引用

2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012

作者： Su, Wen Gao, Xiang Wang, Jing You, Ruibang Key Laboratory of Computer System and Architecture Chinese Academy of Sciences China Institute of Computing Technology Chinese Academy of Sciences China Graduate University Chinese Academy of Sciences China Loongson Technology Corporation Limited China

ISBN: (纸本)9780769547015

With the dramatic increase in network speed during the past ten years, network processing efficiency has been significantly decreased. In this paper, we propose a network accelerating scheme, which employs cache locking method to reduce data and instruction accessing latency. Interrupts handling and buffer maintenance overheads are obviously decreased. Experimental results show that our solution increases about 22% network bandwidth and reduces 10% latency. © 2012 IEEE.

关键词： Locks (fasteners)

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Providing fairness on shared-memory multiprocessors via process scheduling 12

Providing fairness on shared-memory multiprocessors via proc...

引用

12th Joint International Conference on Measurement and Modeling of computer Systems, ACM SIGMETRICS/Performance 2012

作者： Xu, Di Wu, Chenggang Yew, Pen-Chung Li, Jianjun Wang, Zhenjiang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University Chinese Academy of Sciences Beijing China Department of Computer Science and Engineering University of Minnesota at Twin-Cities MN United States Institute of Information Science Academia Sinica Taiwan

ISBN: (纸本)9781450310970

Competition for shared memory resources on multiprocessors is the most dominant cause for slowing down applications and makes their performance varies unpredictably. It exacerbates the need for Quality of Service (QoS) on such systems. In this paper, we propose a fair-progress process scheduling (FPS) policy to improve system fairness. Its strategy is to force the equally-weighted applications to have the same amount of slowdown when they run concurrently. The basic approach is to monitor the progress of all applications at runtime. When we find an application suffered more slowdown and accumulated less effective work than others, we allocate more CPU time to give it a better parity. Our policy also allows different weights to different threads, and provides an effective and robust tuner that allows the OS to freely make tradeoffs between system fairness and higher throughput. Evaluation results show that FPS can significantly improve system fairness by an average of 53.5% and 65.0% on a 4-core processor with a private cache and a 4-core processor with a shared cache, respectively. The penalty is about 1.1% and 1.6% of the system throughput. For memory-intensive workloads, FPS also improves system fairness by an average of 45.2% and 21.1% on 4-core and 8-core system respectively at the expense of a throughput loss of about 2%. © 2012 ACM.

关键词： Throughput

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