检索结果-内蒙古大学图书馆

FLP semantics without circular justifications for general logic programs 26

FLP semantics without circular justifications for general lo...

26th AAAI Conference on Artificial Intelligence and the 24th Innovative Applications of Artificial Intelligence Conference, AAAI-12 / IAAI-12

作者： Shen, Yi-Dong Wang, Kewen State Key Laboratory of Computer Science Institute of Software Chinese Academy of Sciences Beijing 100190 China School of Computing and Information Technology Griffith University Brisbane QLD 4111 Australia

ISBN: (纸本)9781577355687

The FLP semantics presented by (Faber, Leone, and Pfeifer 2004) has been widely used to define answer sets, called FLP answer sets, for different types of logic programs such as logic programs with aggregates, description logic programs (dl-programs), Hex programs, and logic programs with first-order formulas (general logic programs). However, it was recently observed that the FLP semantics may produce unintuitive answer sets with circular justifications caused by self-supporting loops. In this paper, we address the circular justification problem for general logic programs by enhancing the FLP semantics with a level mapping formalism. In particular, we extend the Gelfond-Lifschitz three step definition of the standard answer set semantics from normal logic programs to general logic programs and define for general logic programs the first FLP semantics that is free of circular justifications. We call this FLP semantics the well-justified FLP semantics. This method naturally extends to general logic programs with additional constraints like aggregates, thus providing a unifying framework for defining the well-justified FLP semantics for various types of logic programs. When this method is applied to normal logic programs with aggregates, the well-justified FLP semantics agrees with the conditional satisfaction based semantics defined by (Son, Pontelli, and Tu 2007);and when applied to dl-programs, the semantics agrees with the strongly well-supported semantics defined by (Shen 2011). Copyright © 2012, Association for the Advancement of Artificial Intelligence. All rights reserved.

关键词： Semantics

来源：评论

学校读者我要写书评

暂无评论

Left-to-right tree-to-string decoding with prediction

Left-to-right tree-to-string decoding with prediction

引用

2012 Joint Conference on Empirical Methods in Natural Language Processing and Computational Natural Language Learning, EMNLP-CoNLL 2012

作者： Feng, Yang Liu, Yang Liu, Qun Cohn, Trevor Department of Computer Science University of Sheffield Sheffield United Kingdom State Key Laboratory on Intelligent Technology and Systems Department of Computer Sci. and Tech. Tsinghua University Beijing China Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781937284435

Decoding algorithms for syntax based machine translation suffer from high computational complexity, a consequence of intersecting a language model with a context free grammar. Left-to-right decoding, which generates the target string in order, can improve decoding efficiency by simplifying the language model evaluation. This paper presents a novel left to right decoding algorithm for tree-to-string translation, using a bottom-up parsing strategy and dynamic future cost estimation for each partial translation. Our method outperforms previously published tree-to-string decoders, including a competing left-to-right method. © 2012 Association for Computational Linguistics.

关键词： Context free grammars

来源：评论

学校读者我要写书评

暂无评论

A novel HW/SW partitioning with SIMD instructions for AVS video decoder

A novel HW/SW partitioning with SIMD instructions for AVS vi...

引用

2012 IEEE 7th International Conference on Networking, architecture and Storage, NAS 2012

作者： Chen, Liwei Cong, Ming Huang, Jing Li, Ling Liu, Hongwei Qian, Cheng Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Chinese Academy of Sciences Graduate University Beijing China Loongson Technology Corporation Limited Beijing China

ISBN: (纸本)9780769547220

In this paper, we propose a novel HW/SW partitioning with SIMD instructions for the real-time AVS video decoder. As the SIMD instructions instead of hardware are used to optimize video decoding, our approach achieves an optimal balance between performance and programmability. We implement the proposed HW/SW partitioning on a 32-bit RISC processor with 256-bit vector extension, and evaluate the performance using some standard high-quality streams of AVS. Results show that the video decoding system can support the real-time decoding of AVS HD video streams. © 2012 IEEE.

关键词： Decoding

来源：评论

学校读者我要写书评

暂无评论

Maximum volume clustering: a new discriminative clustering approach

The Journal of Machine Learning Research

引用

The Journal of Machine Learning Research 2013年第1期14卷

作者： Kevin Murphy Bernhard Schölkopf Gang Niu Bo Dai Lin Shang Masashi Sugiyama Google MPI for Intelligent Systems Department of Computer Science Tokyo Institute of Technology Tokyo Japan College of Computing Georgia Institute of Technology Atlanta GA State Key Laboratory for Novel Software Technology Nanjing University Nanjing China

The large volume principle proposed by Vladimir Vapnik, which advocates that hypotheses lying in an equivalence class with a larger volume are more preferable, is a useful alternative to the large margin principle. In this paper, we introduce a new discriminative clustering model based on the large volume principle called maximum volume clustering (MVC), and then propose two approximation schemes to solve this MVC model: A soft-label MVC method using sequential quadratic programming and a hard-label MVC method using semi-definite programming, respectively. The proposed MVC is theoretically advantageous for three reasons. The optimization involved in hard-label MVC is convex, and under mild conditions, the optimization involved in soft-label MVC is akin to a convex one in terms of the resulting clusters. Secondly, the soft-label MVC method possesses a clustering error bound. Thirdly, MVC includes the optimization problems of a spectral clustering, two relaxed k-means clustering and an information-maximization clustering as special limit cases when its regularization parameter goes to infinity. Experiments on several artificial and benchmark data sets demonstrate that the proposed MVC compares favorably with state-of-the-art clustering methods.

关键词： clustering error bound discriminative clustering finite sample stability large volume principle semi-definite programming sequential quadratic programming

来源：评论

学校读者我要写书评

暂无评论

A testability-aware low power architecture

A testability-aware low power architecture

引用

IEEE International SOC Conference

作者： Gang Wang Jian Wang Zi-Chu Qi Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Test power consumption is becoming a major concern in low power integrated circuits (ICs). This paper presents a revised low power compression architecture for scan test. In this paper, the variance in power consumption is used to select test pattern during scan test, and a low power feedback MUX is added to the scan chains. Simulation results by mathematical methods show that the proposed test architecture is promising in reduction of power consumption.

关键词： Power demand computer architecture Switches Clocks Vectors Switching circuits Compaction

来源：评论

学校读者我要写书评

暂无评论

MCC: A Load Balancing and Deadlock Free Interconnect Network for Cache Coherent Chip Multiprocessors

MCC: A Load Balancing and Deadlock Free Interconnect Network...

引用

IEEE International Conference on Computational Science and Engineering, CSE

作者： Liwei Chen Guangfei Zhang Huandong Wang Wenxiang Wang Ling Li Hua Jing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

As the number of cores in chip multiprocessors (CMPs) increases, network-on-chip (NoC) has become a major role in ensuring performance and power scalability. In this paper, we propose multiple-combinational-channel (MCC), a load balancing and deadlock free interconnect network for cache-coherent non-uniform memory accessing (CC-NUMA). In order to make load more balancing and reduce power dissipation, we combine low usage channels and make high usage channels independent and wide enough, since messages transmitted over NoC have different widths and injection rates. Furthermore, based on the in-depth analysis of network traffic, we summarize four traffic patterns and establish several rules to avoid protocol-level deadlock. We implement MCC on a 16-core CMPs, and evaluate the power and performance using universal workloads. The experimental results show that MCC reduces nearly 21% power than multiple-physical-channel with similar throughput. Moreover, MCC improves 10% performance with similar area and power, compared to packet-switching architecture with virtual channels.

关键词： System recovery System-on-a-chip Program processors Bandwidth Load management Throughput Scalability

来源：评论

学校读者我要写书评

暂无评论

Statistical performance comparisons of computers

Statistical performance comparisons of computers

引用

IEEE Symposium on High-Performance computer architecture

作者： Tianshi Chen Yunji Chen Qi Guo Olivier Temam Yue Wu Weiwu Hu State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China INRIA Saclay France Institute of Computing Technology Chinese Academy of Sciences Beijing CN

As a fundamental task in computer architecture research, performance comparison has been continuously hampered by the variability of computer performance. In traditional performance comparisons, the impact of performance variability is usually ignored (i.e., the means of performance measurements are compared regardless of the variability), or in the few cases where it is factored in using parametric confidence techniques, the confidence is either erroneously computed based on the distribution of performance measurements (with the implicit assumption that it obeys the normal law), instead of the distribution of sample mean of performance measurements, or too few measurements are considered for the distribution of sample mean to be normal. We first illustrate how such erroneous practices can lead to incorrect comparisons. Then, we propose a non-parametric Hierarchical Performance Testing (HPT) framework for performance comparison, which is significantly more practical than standard parametric techniques because it does not require to collect a large number of measurements in order to achieve a normal distribution of the sample mean. This HPT framework has been implemented as an open-source software.

关键词： computers Benchmark testing Gaussian distribution Size measurement Data structures

来源：评论

学校读者我要写书评

暂无评论

AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture

AgileRegulator: A hybrid voltage regulator scheme redeeming ...

引用

IEEE Symposium on High-Performance computer architecture

作者： Guihai Yan Yingmin Li Yinhe Han Xiaowei Li Minyi Guo Xiaoyao Liang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Department of Computer Science and Engineering Shanghai Jiaotong University China

The widening gap between the fast-increasing transistor budget but slow-growing power delivery and system cooling capability calls for novel architectural solutions to boost energy efficiency. Leveraging the fact of surging “dark silicon” area, we propose a hybrid scheme to use both on-chip and off-chip voltage regulators, called “AgileRegulator”, for a multicore system to explore both coarse-grain and fine-grain power phases. We present two complementary algorithms: Sensitivity-Aware Application Scheduling (SAAS) and Responsiveness-Aware Application Scheduling (RAAS) to maximally achieve the energy saving potential of the hybrid regulator scheme. Experimental results show that the hybrid scheme achieves performance-energy efficiency close to per-core DVFS, without imposing much design cost. Meanwhile, the silicon overhead of this scheme is well contained into the “dark silicon”. Unlike other application specific schemes based on accelerators, the proposed scheme itself is a simple and universal solution for chip area and energy trade-offs.

关键词： System-on-a-chip Regulators Silicon Bandwidth Memory management Tuning Multicore processing

来源：评论

学校读者我要写书评

暂无评论

A lightweight hybrid hardware/software approach for object-relative memory profiling

A lightweight hybrid hardware/software approach for object-r...

引用

IEEE International Symposium on Performance Analysis of Systems and Software

作者： Licheng Chen Zehan Cui Yungang Bao Mingyu Chen Yongbing Huang Guangming Tan Graduate School of Chinese Academy of Sciences China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781467311434

Memory profiling is the process of collecting memory address traces during the execution of a program, then analyzing and characterizing the memory behavior of the program offline. With the trend that there will be more and more cores integrated in a processor chip, the “Memory Wall” problem will become more serious in the chip multiprocessor (CMP) system. Thus accurate and effective memory profiling is becoming one of the keys to identify the source of memory system bottlenecks. A large body of work has been contributed to memory profiling, however, most adopts instrumentation, simulator which suffers heavy overhead, or hardware performance counter which is lack of detail trace information. Furthermore, correlating the raw memory address traces with object-relative information allows us to separate regular pattern for certain object from the irregular mixed, thus helps the optimization. In this paper, we propose a lightweight hybrid hardware/software approach for object-relative memory profiling. We monitor physical memory addresses through hardware snooping with negligible overhead; meanwhile we dump Linux kernel page tables of processes, as well as object-relative memory allocation information. Our approach supports not only to collect applications' full memory traces with detail object relative information, but also to identify hardware-generated memory accesses such as page memory walks due to TLB miss at object level. The experimental results on real system show that our approach is highly accurate (the largest error is 2.04%) and low overhead (the average overhead is 1.60%). Furthermore, we profile two multi-thread applications in detail, and successfully identity hot TLB-miss objects. With object-targeted optimization, we can improve applications' performance by nearly 6.86%.

关键词： Kernel Hardware Monitoring Optimization Linux Arrays

来源：评论

学校读者我要写书评

暂无评论

Off-path leakage power aware routing for SRAM-based FPGAs 12

Off-path leakage power aware routing for SRAM-based FPGAs

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Keheng Huang Yu Hu Xiaowei Li Bo Liu Hongjin Liu Jian Gong Graduate University of Chinese Academy of Sciences China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Control Laboratory Beijing Institute of Control Engineering China

ISBN: (纸本)9783981080186

As the feature size and threshold voltage reduce, leakage power dissipation becomes an important concern in SRAM-based FPGAs. This work focuses on reducing the leakage power in routing resources, and more specifically, the leakage power dissipated in the used part of FPGA device, which is known as the active leakage power. We observe that the leakage power in off-path transistors takes up most of the active leakage power in multiplexers that control routing, and strongly depends on Hamming distance between the state of the on-path input and the states of the off-path inputs. Hence, an off-path leakage power aware routing algorithm is proposed to minimize Hamming distance between the state of on-path input and the states of off-path inputs for each multiplexer. Experimental results on MCNC benchmark circuits show that, compared with the baseline VPR technique, the proposed off-path leakage aware routing algorithm can reduce active leakage power in routing resources by 16.79%, and the increment of critical-path delay is only 1.06%.

关键词： Multiplexing Routing Wires Transistors Field programmable gate arrays Timing Vectors

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：