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Green challenges to system software in data centers

中国计算机科学前沿 2011年第3期5卷 353-368页

作者： Yuzhong SUN Yiqiang ZHAO Ying SONG Yajun YANG Haifeng FANG Hongyong ZANG Yaqiong LI Yunwei GAO Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100190 China

With the increasing demand and the wide application of high performance commodity multi-core processors,both the quantity and scale of data centers grow dramatically and they bring heavy energy *** and engineers have applied much effort to reducing hardware energy consumption,but software is the true consumer of power and another key in making better use of *** software is critical to better energy utilization,because it is not only the manager of hardware but also the bridge and platform between applications and *** this paper,we summarize some trends that can affect the efficiency of data ***,we investigate the causes of software *** on these studies,major technical challenges and corresponding possible solutions to attain green system software in programmability,scalability,efficiency and software architecture are ***,some of our research progress on trusted energy efficient system software is briefly introduced.

关键词： green software multi-core data center power efficient system software

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An architecture description language based on dynamic description logics

An architecture description language based on dynamic descri...

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7th IFIP International Conference on Intelligent Information Processing, IIP 2012

作者： Wang, Zhuxiao Peng, Hui Guo, Jing Zhang, Ying Wu, Kehe Xu, Huan Wang, Xiaofeng School of Control and Computer Engineering State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources North China Electric Power University Beijing 102206 China Education Technology Center Beijing International Studies University Beijing 100024 China National Computer Network Emergency Response Technical Team/Coordination Center of China Beijing 100029 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

ISBN: (纸本)9783642328909

ADML is an architectural description language based on Dynamic Description Logic for defining and simulating the behavior of system architecture. ADML is being developed as a new formal language and/or conceptual model for representing the architectures of concurrent and distributed systems, both hardware and software. ADML embraces dynamic change as a fundamental consideration, supports a broad class of adaptive changes at the architectural level, and offers a uniform way to represent and reason about both static and dynamic aspects of systems. Because the ADML is based on the Dynamic Description Logic DDL( (D)), which can represent both dynamic semantics and static semantics under a unified logical framework, architectural ontology entailment for the ADML languages can be reduced to knowledge base satisfiability in DDL( (D)), and dynamic description logic algorithms and implementations can be used to provide reasoning services for ADML. In this article, we present the syntax of ADML, explain its underlying semantics using the Dynamic Description Logic DDL( (D)), and describe the core architecture description features of ADML. © 2012 IFIP International Federation for Information Processing.

关键词： Formal languages

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Left-to-Right Tree-to-String Decoding with Prediction 12

Left-to-Right Tree-to-String Decoding with Prediction

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Conference on Empirical Methods in Natural Language Processing

作者： Yang Feng Yang Liu Qun Liu Trevor Cohn Department of Computer Science The University of Sheffield Sheffield UK State Key Laboratory on Intelligent Technology and Systems Tsinghua National Laboratory for Information Science and Technology Department of Computer Sci. and Tech. Tsinghua University Beijing China Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781622765034

Decoding algorithms for syntax based machine translation suffer from high computational complexity, a consequence of intersecting a language model with a context free grammar. Left-to-right decoding, which generates the target string in order, can improve decoding efficiency by simplifying the language model evaluation. This paper presents a novel left to right decoding algorithm for tree-to-string translation, using a bottom-up parsing strategy and dynamic future cost estimation for each partial translation. Our method outperforms previously published tree-to-string decoders, including a competing left-to-right method.

关键词： modelling languages DECODING decoding algorithm machine translation syntax context-free grammars

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Delay-bounded Sink Mobility in Wireless Sensor Networks

Delay-bounded Sink Mobility in Wireless Sensor Networks

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IEEE International Conference on Communications

作者： Yu Gu Yusheng Ji Jie Li Biao Han Baohua Zhao Information Systems Architecture Science Research Division National Institute of Informatics Department of Computer Science University of Tsukuba Tsukuba Science City State Key Laboratory of Networking and Switching Technology

ISBN: (纸本)9781457720529

This paper exploits sink mobility to prolong the network lifetime in wireless sensor networks (WSNs) where the information delay caused by moving the sink should be bounded. We build a unified framework for analyzing this joint sink mobility and routing problem. We offer a mathematical modeling that is general and captures diversified issues, e.g. sink mobility, routing, delay, etc. We discuss the induced subproblems and present efficient solutions for them. Then, we generalize these solutions and propose a polynomial-time optimal algorithm for the origin problem. In simulations, we show the benefits of involving a mobile sink. We also show that the impact of the delay bound on the network lifetime.

关键词： Sinks Wireless sensor networks Routing Problem mobility mathematical modeling

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Productive information system oriented trust chain scheme

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Telkomnika 2012年第5期10卷 1093-1100页

作者： Tian, Li-Ye Shen, Chang-Xiang Department of Electronic and Information Engineering Naval Aeronautical and Astronautical University China Beijing Key Laboratory of Trusted Computing College of Computer Science and Technology Beijing University of Technology China State Key Laboratory of Information Security Chinese Academy of Sciences Institute of Software China

Productive information system has high-level security requirements, but Trusted computing Group's solution of trust chain isn't competent. After analysis and comparison of two different trust transfer ways, a new trust chain scheme was designed and its architecture was shown. With independent TPCM as a trust root, this scheme combined the advantages of linear and radial transfer. So that stronger cryptographic algorithm could be adopted by TPCM and applications' trust attenuation decreased a lot. This scheme was described formally by 6 linear temporal logic rules. It was proved that based on these rules, this scheme could transfer trust from trust root to applications. Meanwhile, it could actively report and handle exceptions in trust chain building and system running. Conclusion and future work were given at the end of this manuscript. © 2012 Universitas Ahmad Dahlan.

关键词： Chains

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Design for Testability Features of Godson-3 Multicore Microprocessor

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Journal of computer Science & technology 2011年第2期26卷 302-313页

作者：齐子初刘慧李向库胡伟武 Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Chinese Academy of Sciences Loongson Technologies Corporation Limited

This paper describes the design for testability （DFT） challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar （SMOC） on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism （TAM） is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

关键词： DFT （design for testability） TAM （test access mechanism） multicore processor low power test

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Dawning Nebulae:A PetaFLOPS Supercomputer with a Heterogeneous Structure

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Journal of computer Science & technology 2011年第3期26卷 352-362页

作者：孙凝辉邢晶霍志刚谭光明熊劲李波马灿 Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences

Dawning Nebulae is a heterogeneous system composed of 9280 multi-core x86 CPUs and 4640 NVIDIA Fermi GPUs. With a Linpack performance of 1.271 petaFLOPS, it was ranked the second in the TOP500 List released in June 2010. In this paper, key issues in the system design of Dawning Nebulae are introduced. System tuning methodologies aiming at petaFLOPS Linpack result are presented, including algorithmic optimization and communication improvement. The design of its file I/O subsystem, including HVFS and the underlying DCFS3, is also described. Performance evaluations show that the Linpack efficiency of each node reaches 69.89%, and 1024-node aggregate read and write bandwidths exceed 100 GB/s and 70 GB/s respectively. The success of Dawning Nebulae has demonstrated the viability of CPU/GPU heterogeneous structure for future designs of supercomputers.

关键词： supercomputer heterogeneous systems performance evaluation

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Computation pattern driven reuse of manual optimizations for GPGPUs

Computation pattern driven reuse of manual optimizations for...

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2011 12th International Conference on Parallel and Distributed computing, Applications and Technologies, PDCAT 2011

作者： Xu, Shixiong Han, Dongni Chen, Li Key Laboratory of Computer System and Architecture Institute of Computing Technology University of Chinese Beijing China

ISBN: (纸本)9780769545646

The wide application of General Purpose Graphic Processing Units (GPGPUs) results in large manual efforts on porting and optimizing algorithms on them. However, most existing automatic ways of generating GPGPU code fail to conduct optimization strategies regarding a specific computation and to reuse constantly evolving manual optimizations. In this paper, we present a computation pattern driven approach for computation-specific GPGPU code generation and optimization, which in turn reuses manual optimizations to a certain extent. We suggest language extensions to OpenMP, high-level data structure attributes, in order to assist the process of computation pattern matching and to help give users intuitive performance tuning parameters in the view of data structure attributes. We illustrate the feasibility of this approach through three important computation dwarfs, which are dense matrix, sparse matrix, and structured mesh computation in scientific computing. We also build a prototype OpenMP-to-CUDA translator that consists of computation pattern recognition and code template instantiation. The experimental results demonstrate the performance benefits of computation pattern driven method. To our best knowledge, it is the first work on reusing manual optimizations for GPGPUs with computation pattern driven approach. © 2011 IEEE.

关键词： Data structures

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Building algorithmically nonstop fault tolerant MPI programs

Building algorithmically nonstop fault tolerant MPI programs

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18th International Conference on High Performance computing, HiPC 2011

作者： Wang, Rui Yao, Erlin Chen, Mingyu Tan, Guangming Balaji, Pavan Buntinas, Darius State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Mathematics and Computer Science Argonne National Laboratory United States

ISBN: (纸本)9781457719516

With the growing scale of high-performance computing (HPC) systems, today and more so tomorrow, faults are a norm rather than an exception. HPC applications typically tolerate fail-stop failures under the stop-and-wait scheme, where even if only one processor fails, the whole system has to stop and wait for the recovery of the corrupted data. It is now a more-or-less accepted fact that the stop-and-wait scheme will not scale to the next generation of HPC systems. Inspired by the previous stop-and-wait algorithm-based fault tolerance (ABFT) recovery technique, we propose in this paper a nonstop fault tolerance scheme at the application level and describe its implementation. When failure occurs during the execution of applications, we do not stop to wait for the recovery of the corrupted node;instead, we replace it with the corresponding redundant node and continue the execution. At the end of execution, the correct solution can be recovered algorithmically at a very low cost. In order to implement the scheme, some new fault-tolerant features of the Message Passing Interface (MPI) have been investigated and utilized in the MPICH implementation of MPI. We also describe a case study using High Performance Linpack (HPL) with these new features and evaluate the performance of both our new scheme and ABFT recovery. Experimental results show the advantage of our new scheme over ABFT recovery even in a small scale. © 2011 IEEE.

关键词： Message passing

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Using Data-Level Parallelism to Accelerate Instruction -Level Redundancy

Using Data-Level Parallelism to Accelerate Instruction -Leve...

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World Automation Congress

作者： Yu Hu Zhong liang Chen Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology CAS Beijing 100190 China Department of Electrical and Computer Engineering Northeastern University Boston MA 02115 USA

ISBN: (纸本)9781467344975

Instruction-level redundancy is an effective scheme to reduce the susceptibility of microprocessors to soft errors, offering high error detection and recovery capability;however, it usually incurs significant performance degradation due to resource racing. Motivated by the fact that narrow-width operands are commonly seen in applications, we exploit data-level parallelism to accelerate instruction-level redundancy. For the instructions within sphere of replication (SoR) of data-level redundancy, normal and redundant versions of the narrow-width operand of the instruction are folded into one register to share the same functional unit during execution hence alleviating resource racing. The other instructions are all protected by instructionlevel redundancy. We run SPECint2000 benchmarks on a modified version of SimpleScalar simulator, and synthesize the extra hardware to evaluate area overhead of the proposed pipeline. Experimental results show that our acceleration scheme outperforms conventional instruction-level redundancy by 13% in IPC. Besides, the extra area overhead is negligible.

关键词： keywords Data-level redundancy Instruction-level redundancy Narrow-width value Sphere of replication

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