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Empirical design bugs prediction for verification

Empirical design bugs prediction for verification

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作者： Guo, Qi Chen, Tianshi Shen, Haihua Chen, Yunji Wu, Yue Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Beijing 100049 China Loongson Technologies Corporation Limited Beijing 100190 China

ISBN: (纸本)9783981080179

Coverage model is the main technique to evaluate the thoroughness of dynamic verification of a Design-under-Verification (DUV). However, rather than achieving a high coverage, the essential purpose of verification is to expose as many bugs as possible. In this paper, we propose a novel verification methodology that leverages the early bug prediction of a DUV to guide and assess related verification process. To be specific, this methodology utilizes predictive models built upon artificial neural networks (ANNs), which is capable of modeling the relationship between the high-level attributes of a design and its associated bug information. To evaluate the performance of constructed predictive model, we conduct experiments on some open source projects. Moreover, we demonstrate the usability and effectiveness of our proposed methodology via elaborating experiences from our industrial practices. Finally, discussions on the application of our methodology are presented. © 2011 EDAA.

关键词： Neural networks

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Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs

Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-...

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Asian Test Symposium (ATS)

作者： Keheng Huang Yu Hu Xiaowei Li Gengxin Hua Hongjin Liu Bo Liu State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Beijing Institute of Control Engineering China

As the feature size of FPGA shrinks to nanometers, SRAM-based FPGAs are more vulnerable to soft errors. During logic synthesis, reliability of the design can be improved by introducing logic masking effect. In this work, we observe that there are a lot of not-fully occupied look-up tables (LUTs) after logic synthesis. Hence, we propose a functional equivalent class based soft error mitigation scheme to exploit free LUT entries in the circuit. The proposed technique replaces not fully-occupied LUTs with corresponding functional equivalent classes, which can improve the reliability while preserve the functionality of the design. Experimental results show that, compared with the baseline ABC mapper, the proposed technique can reduce the soft error rate by 21%, and the critical-path delay increase is only 4.25%.

关键词： Table lookup Circuit faults Forward error correction Field programmable gate arrays Vectors Reliability engineering

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Optimizing MPI alltoall communication of large messages in multicore clusters

Optimizing MPI alltoall communication of large messages in m...

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2011 12th International Conference on Parallel and Distributed computing, Applications and Technologies, PDCAT 2011

作者： Li, Qiang Huo, Zhigang Sun, Ninghui Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Chinese Academy of Sciences Graduate University Beijing 100049 China

ISBN: (纸本)9780769545646

MPI Alltoall communication is widely used in many high performance computing (HPC) applications. In Alltoall communication, each process sends a distinct message to all other participating processes. In multicore clusters, processes within a node simultaneously contend for the same network resource of the node in Alltoall communication. However, many small synchronization messages are required in Alltoall communication of large messages. With the contention, their latency is orders of magnitude larger than that without contention. As a result, the synchronization overhead is significantly increased and accounts for a large proportion to the whole latency of Alltoall communication. In this paper, we analyse the considerable overhead of synchronization messages. Base on the analysis, an optimization is presented to reduce the number of synchronization messages from 3N to 2√N. Evaluations on a 240-core cluster show that the performance is improved by almost constant ratio, which is mainly determined by message size and independent of system scale. The performance of Alltoall communication is improved by 25% for 32K and 64K bytes messages. For FFT application, performance is improved by 20%. © 2011 IEEE.

关键词： Synchronization

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Network content security evaluation method analysis

Network content security evaluation method analysis

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2011 2nd International Conference on Theoretical and Mathematical Foundations of computer Science, ICTMF 2011

作者： Zhang, Dongyan Yin, Lihua Chen, Hongsong Dept. of Computer Science and Technology University of Science and Technology Beijing Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications Beijing China

ISBN: (纸本)9783642249983

The network content security system of Internet information requires a controlling force over information flows which allows the access to some information and prohibits some other information. The complexity of Internet information flows makes it difficult to control precisely over the Internet. Consequently, corresponding evaluation shall be conducted over all kinds of controlling methods. In the paper, precision rate and error rate metrics are proposed to evaluate the network content security system. Consequently we use the evaluation methods in intrusion detection and information retrieval for reference to evaluate the network content security system. We take a deep analysis for the evaluation methods from two aspects which are "monotony" of evaluation methods and the sensibility of evaluation methods and point out which of these methods are applicable to network content security controlling system. At last, we state briefly the application range of CID, ECC, NAMI and other metrics. © 2011 Springer-Verlag.

关键词： Access control

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A resilient on-chip router design through data path salvaging 11

A resilient on-chip router design through data path salvagin...

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Asia and South Pacific Design Automation Conference

作者： Cheng Liu Lei Zhang Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424475162

Very large scale integrated circuits typically employ Network-on-Chip (NoC) as the backbone for on-chip communication. As technology advances into the nanometer regime, NoCs become more and more susceptible to permanent faults such as manufacturing defects, device wear-out, which hinder the correct operations of the entire system. Therefore, effective fault-tolerant techniques are essential to improve the reliability of NoCs. Prior work mainly focuses on introducing redundancies, which can't achieve satisfactory reliability and also involve large hardware overhead, especially for data path components. In this paper, we propose fine-grained data path salvaging techniques by splitting data path components, i.e., links, input buffers and crossbar into slices, instead of introducing redundancies. As long as there is one fault-free slice for each component, the router can be functional. Experimental results show that the proposed solution achieves quite high reliability with graceful performance degradation even under high fault rate.

关键词： Fault tolerant systems Redundancy Pipelines Routing Circuit faults

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Wear rate leveling: Lifetime enhancement of PRAM with endurance variation 11

Wear rate leveling: Lifetime enhancement of PRAM with endura...

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Design Automation Conference

作者： Jianbo Dong Lei Zhang Yinhe Han Ying Wang Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781450306362

The limited write endurance of phase change random access memory (PRAM) is one of the major obstacles for PRAM-based main memory. Wear leveling techniques were proposed to extend its lifetime by balancing writes traffic. Another important concern that need to be considered is endurance variation in PRAM chips. When different PRAM cells have distinct endurance, balanced writes will result in lifetime degradation due to the weakest cells. Instead of balancing writes traffic, in this paper we propose wear rate leveling (WRL), a variant of wear leveling, to balance wear rates (i.e., writes traffic/edudrance) of cells across the PRAM chip. After investigating writing behavior of applications and endurance variation, we propose an architecture-level WRL mechanism. Moreover, there is an important tradeoff between endurance improvement and swapping data volume. To co-optimize endurance and swapping, a novel algorithm, Max Hyper-weight Rematching, is proposed to maximize PRAM lifetime and minimize performance degradation. Experimental results show 19x endurance improvement to prior Wear Leveling.

关键词： Phase change random access memory Writing Programming Degradation Prediction algorithms Systematics Complexity theory

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Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip 11

Vertical interconnects squeezing in symmetric 3D mesh Networ...

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Asia and South Pacific Design Automation Conference

作者： Cheng Liu Lei Zhang Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424475162

Three-dimensional (3D) integration and Network-on-Chip (NoC) are both proposed to tackle the on-chip interconnect scaling problems, and extensive research efforts have been devoted to the design challenges of combining both. Through-silicon via (TSV) is considered to be the most promising technology for 3D integration, however, TSV pads distributed across planar layers occupy significant chip area and result in routing congestions. In addition, the yield of 3D integrated circuits decreased dramatically as the number of TSVs increases. For symmetric 3D mesh NoC, we observe that the TSVs' utilization is pretty low and adjacent routers rarely transmit packets via their vertical channels (i.e. TSVs) at the same time. Based on this observation, we propose a novel TSV squeezing scheme to share TSVs among neighboring router in a time division multiplex mode, which greatly improves the utilization of TSVs. Experimental results show that the proposed method can save significant TSV footprint with negligible performance overhead.

关键词： Through-silicon vias Three dimensional displays Pipelines Routing Throughput computer architecture System-on-a-chip

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基于状态恢复的追踪信号选择方法

基于状态恢复的追踪信号选择方法

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第七届中国测试学术会议

作者： Cheng Yun 程云 Li Huawei 李华伟 Li Xiaowei 李晓维 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of 计算机体系结构国家重点实验室中国科学院计算技术研究所北京100190 中国科学院研究生院北京100049 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of 计算机体系结构国家重点实验室中国科学院计算技术研究所北京100190

硅后调试成为集成电路设计中关键环节之一，可调试性设计也得到了工业界广泛应用。本文介绍了一种在基于追踪的可调试性设计中利用状态恢复原理选择追踪信号的方法，并编程实现了状态恢复算法和基于概率的追踪信号选择算法。进一步地，... 详细信息

硅后调试成为集成电路设计中关键环节之一，可调试性设计也得到了工业界广泛应用。本文介绍了一种在基于追踪的可调试性设计中利用状态恢复原理选择追踪信号的方法，并编程实现了状态恢复算法和基于概率的追踪信号选择算法。进一步地，本文在基于概率的追踪信号选择基础上，提出了基于模拟的追踪信号选择方法，通过模拟来得到更实际的概率初值以提高状态恢复率估计的准确性。实验结果表明，利用状态恢复原理选择追踪信号的方法可以有效的提高硅后调试的可观测性。

关键词：集成电路设计硅后调试状态恢复算法追踪信号选择

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基于敏感度分析的异构众核处理器能效管理方法

基于敏感度分析的异构众核处理器能效管理方法

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第七届中国测试学术会议

作者： Jun Ma 马君 Guihai Yan 鄢贵海 Yinhe Han 韩银和 Xiaowei Li 李晓维 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of 中国科学院计算技术研究所计算机体系结构国家重点实验室(筹) 北京100190 中国科学院研究生院北京 100190 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of 中国科学院计算技术研究所计算机体系结构国家重点实验室(筹) 北京100190

随着集成电路设计和半导体工艺的发展，以及人们对计算需求的不断提高，处理器的结构也逐渐由单核、多核向众核演化。与此同时，单个多核处理器芯片的功耗也迅速上升。但限于片上供电及散热等因素的限制，功耗成为限制众核处理器性能提... 详细信息

随着集成电路设计和半导体工艺的发展，以及人们对计算需求的不断提高，处理器的结构也逐渐由单核、多核向众核演化。与此同时，单个多核处理器芯片的功耗也迅速上升。但限于片上供电及散热等因素的限制，功耗成为限制众核处理器性能提升的主要瓶颈。因此，如何在功耗受限的前提下充分发挥众核处理器的计算能力，即高效的能耗管理方法，是当下计算机体系结构设计的关键问题之一。现有的管理手段主要有动态电压频率调节、多线程技术及异构多核架构。但是如何有效地将这些技术有机结合来协同管理功耗及提升能效还有待研究。本文针对一种异构众核体系结构，利用敏感度分析的方法来指导能效管理。通过分析工作频率、线程数在不同异构架构上的能效边际效益，来择优激活某些处理器核，确定各个核的工作频率，以及分配并行程序的线程数量。

关键词：集成电路异构众核处理器能效管理敏感度分析边际效益

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TSV-SAFE:一种抑制三维集成电路硅通孔电迁移效应的可靠性设计框架

TSV-SAFE:一种抑制三维集成电路硅通孔电迁移效应的可靠性设计框架

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第七届中国测试学术会议

作者： Cheng Yuanqing 成元庆 Zhang Lei 张磊 Han Yinhe 韩银和 Li Xiaowei 李晓维 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of 中国科学院计算技术研究所计算机体系结构国家重点实验室(筹) 北京100190 中国科学院研究生院北京 100190 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of 中国科学院计算技术研究所计算机体系结构国家重点实验室(筹) 北京100190

三维集成电路是通过硅通孔将多个相同或不同工艺的晶片上下堆叠并进行垂直集成的新兴芯片集成技术。通过这种集成,芯片可获得更小的外形尺寸、更高的片上晶体管集成密度、单片上能集成更多的功能模块以及更高的互连性能等显著优点。然而... 详细信息

三维集成电路是通过硅通孔将多个相同或不同工艺的晶片上下堆叠并进行垂直集成的新兴芯片集成技术。通过这种集成,芯片可获得更小的外形尺寸、更高的片上晶体管集成密度、单片上能集成更多的功能模块以及更高的互连性能等显著优点。然而,三维集成电路也带来了诸如TSV电迁移效应等新挑战。本文提出了一种抑制TSV电迁移效应的可靠性设计方法。首先,针对镀铜气泡、绑定非对齐和绑定界面尘埃沾染等TSV缺陷,分析了制造缺陷和电迁移效应之间的关系。通过观察发现,制造缺陷在加剧电迁移效应的同时还会影响TSV的阻值。然后,本文提出了TSV-SAFE(TSV Self-healing architecture For Electro-migration)可靠性设计框架抑制电迁移效应。实验中,本文构建了一个由两层电路组成的3D芯片仿真平台。实验结果表明,采用本文所提出的技术,TSV的平均无故障时间(MTTF)平均增加了70倍,而由此带来的硬件面积开销不超过全芯片面积的1％。

关键词：三维集成电路电迁移效应可靠性设计自修复技术

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