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Indexing Techniques of Distributed Ordered Tables： A Survey and Analysis

Journal of computer Science & technology 2018年第1期33卷 169-189页

作者： Chen Feng Chun-Dian Li Rui Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China~TT ' University of Chinese Academy of Sciences Beijing 100049 China Tencent Inc. Beijing 100080 China

Many NoSQL （Not Only SQL） databases were proposed to store and query on a huge amount of data. Some of them like BigTable, PNUTS, and HBase, can be modeled as distributed ordered tables （DOTs）. Many additional indexing techniques have been presented to support queries on non-key columns for DOTs. However, there was no comprehensive analysis or comparison of these techniques, which brings troubles to users in selecting or proposing a proper indexing technique for a certain workload. This paper proposes a taxonomy based on six indexing issues to classify indexing techniques on DOTs and provides a comprehensive review of the state-of-the-art techniques. Based on the taxonomy, we propose a performance model named QSModel to estimate the query time and storage cost of these techniques and run experiments on a practical workload from Tencent to evaluate this model. The results show that the maximum error rates of the query time and storage cost are 24.2% and 9.8% respectively. Furthermore, we propose IndexComparator, an open source project that implements representative indexing techniques. Therefore, users can select the best-fit indexing technique based on both theoretical analysis and practical experiments.

关键词： database Not Only SQL （NoSQL） range query indexing

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Evaluating and Constraining Hardware Assertions with Absent Scenarios

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Journal of computer Science & technology 2020年第5期35卷 1198-1216页

作者： Hui-Na Chao Hua-Wei Li Xiaoyu Song Tian-Cheng Wang Xiao-Wei Li State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China Peng Cheng Laboratory Shenzhen 518052China Department of Electrical and Computing Engineering Portland State UniversityPortlandOR 97207U.S.A.

Mining from simulation data of the golden model in hardware design verification is an effective solution to assertion *** the simulation data is inherently incomplete,it is necessary to evaluate the truth values of the mined *** paper presents an approach to evaluating and constraining hardware assertions with absent scenarios.A Belief-fail Rate metric is proposed to predict the truth/falseness of generated *** considering both the occurrences of free variable assignments and the conflicts of absent scenarios,we use the metric to sort true assertions in higher ranking and false assertions in lower *** Belief-failRate guided assertion constraining method leverages the quality of generated *** experimental results show that the Belief-failRate framework performs better than the existing *** addition,the assertion evaluating and constraining procedure can find more assertions that cover new design functionality in comparison with the previous methods.

关键词： hardware formal verification assertion generation data mining assertion evaluation assertion coverage

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Prevention from Soft Errors via architecture Elasticity

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Journal of computer Science & technology 2014年第2期29卷 247-254页

作者：尹一笑陈云霁郭崎陈天石 State Key Lab of Computer Architecture and Microprocessor Research Center Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences Loongson Technology Corporation Limited IBM Research-China

Due to the decreasing threshold voltages, shrinking feature size, as well as the exponential growth of on-chip transistors, modern processors are increasingly vulnerable to soft errors. However, traditional mechanisms of soft error mitigation take actions to deal with soft errors only after they have been detected. Instead of the passive responses, this paper proposes a novel mechanism which proactively prevents from the occurrence of soft errors via architecture elasticity. In the light of a predictive model, we adapt the processor architectures h01istically and dynamically. The predictive model provides the ability to quickly and accurately predict the simulation target across different program execution phases on any architecture configurations by leveraging an artificial neural network model. Experimental results on SPEC CPU 2000 benchmarks show that our method inherently reduces the soft error rate by 33.2% and improves the energy efficiency by 18.3% as compared with the static configuration processor.

关键词： soft error energy efficiency architecture elasticity

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TSV Minimization for Circuit Partitioned 3D SoC Test Wrapper Design

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Journal of computer Science & technology 2013年第1期28卷 119-128页

作者： Yuan-Qing Cheng Lei Zhang Yin-He Han Xiao-Wei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100049 China

Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs. Thre dimensional （3D） integration has been proposed to sustain Moore＇s law by incorporating through-silicon vias （TSVs） to integrate different circuit modules in the vertical direction, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-on- Chips （SoCs）. Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. In addition, vertical interconnects, i.e., TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding pads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively. It is composed of two steps, i.e., scan chain allocation and functional input/output insertion, both of which can reduce TSV count significantly. Through extensive experimental evaluations, it is shown that reduce the number of test TSVs dramatically, i.e., as much as 26% in comparison with the intuitive method. the test wrapper chain structure designed by our method can 60.5% reductions in comparison with the random method and

关键词： three-dimensional system-on-chip test wrapper chain through-silicon vias optimization

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Heralded path-entangled NOON states generation from a reconfigurable photonic chip

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Chinese Physics B 2022年第6期31卷 358-362页

作者： Xinyao Yu Pingyu Zhu Yang Wang Miaomiao Yu Chao Wu Shichuan Xue Qilin Zheng Yingwen Liu Junjie Wu Ping Xu Institute for Quantum Information&State Key Laboratory of High Performance Computing College of Computer Science and TechnologyNational University of Defense TechnologyChangsha 410073China

Maximal multi-photon entangled states,known as NOON states,play an essential role in quantum *** the number of photons growing,NOON states are becoming increasingly powerful and advantageous for obtaining supersensitive and super-resolved *** this paper,we propose a universal scheme for generating three-and four-photon path-entangled NOON states on a reconfigurable photonic chip via photons subtracted from pairs and detected by heralding *** method is postselection free,enabling phase supersensitive measurements and sensing at the Heisenberg *** NOON-state generator allows for integration of quantum light sources as well as practical and portable precision phase-related measurements.

关键词： path-entangled NOON state phase measurement

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Constructing Edge-Colored Graph for Heterogeneous Networks

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Journal of computer Science & technology 2015年第5期30卷 1154-1160页

作者：侯睿武继刚陈亚文张海波隋秀峰 School of Computer Science and Software Engineering Tianjin Polytechnic University Tianjin 300387 China State Key Laboratory of Computer Architecture~ Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Department of Computer Science University of Otago Dunedin 9054 New Zealand

In order to build a fault-tolerant network, heterogeneous facilities are arranged in the network to prevent homogeneous faults from causing serious damage. This paper uses edge-colored graph to investigate the features of a network topology which is survivable after a set of homogeneous devices malfunction. We propose an approach to designing such networks under arbitrary parameters. We also show that the proposed approach can be used to optimize inter-router connections in network-on-chip to reduce the additional consum!otion of energy and time delay.

关键词： network reliability homogeneous fault fault tolerance reconfigurable system network-on-chip

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Practical two-dimensional correlation power analysis and its backward fault-tolerance

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Science China(Information Sciences) 2017年第6期60卷 257-259页

作者： An WANG Wenjing HU Weina TIAN Guoshuang ZHANG Liehuang ZHU School of Computer Science Beijing Institute of Technology State Key Laboratory of Cryptology The Institution of Beijing Jinghang Computing Communication College of Bioengineering Beijing Polytechnic Science and Technology on Information Assurance Laboratory

Side-channel analysis was introduced by Kocher et al.[1,2]which marked the outbreak of this new research field in the applied cryptography ***,many side-channel analysis methods have been published,for example,correla... 详细信息

关键词： DCPA In Practical two-dimensional correlation power analysis and its backward fault-tolerance CCA rate TP

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CPicker： Leveraging Performance-Equivalent Configurations to Improve Data Center Energy Efficiency

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Journal of computer Science & technology 2018年第1期33卷 131-144页

作者： Fa-Qiang Sun Gui-Hai Yan Xin He Hua-Wei Li Yin-He Han State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China National Computer Network Emergency Response Technical Team of China Beijing 100029 China University of Chinese Academy of Sciences Beijing 100049 China

The poor energy proportionality of server is seen as the principal source for low energy efficiency of modern data centers. We find that different resource configurations of an application lead to similar performance, but have distinct energy consumption. We call this phenomenon as ＂performance-equivalent resource configurations （PERC）＂, and its performance range is called equivalent region （ER）. Based on PERC, one basic idea for improving energy efficiency is to select the most efficient configuration from PERC for each application. However, it cannot support every application to obtain optimal solution when thousands of applications are run simultaneously on resource-bounded servers. Here we propose a heuristic scheme, CPicker, based on genetic programming to improve energy efficiency of servers. To speed up convergence, CPicker initializes a high quality population by first choosing configurations from regions that have high energy variation. Experiments show that CPicker obtains above 17% energy efficiency improvement compared with the greedy approach, and less than 4% efficiency loss compared with the oracle case.

关键词： performance equivalence energy efficiency data center power management dynamic voltage and frequencyscaling （DVFS）

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Revisiting benchmarking principles and methodologies for big data benchmarking 6th

Revisiting benchmarking principles and methodologies for big...

引用

6th Workshop on Big Data Benchmarks, Performance Optimization, and Emerging Hardware, BPOE 2015

作者： Zhao, Liutao Gao, Wanling Jin, Yi Key Laboratory of Cloud Computing Technology and Application Beijing Computing Center Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783319290058

Benchmarking as yardsticks for system design and evaluation, has developed a long period and plays a pivotal role in many domains, such as database systems and high performance computing. Through prolonged and unremitting efforts, benchmarks on these domains have been reaching their maturity gradually. However, in terms of emerging scenarios of big data, its different properties in data volume, data types, data processing requirements and techniques, make that existing benchmarks are rarely appropriate for big data systems and further make us wonder how to define a good big data benchmark. In this paper, we revisit successful benchmarks in other domains from two perspectives: benchmarking principles which define fundamental rules, and methodologies which guide the benchmark constructions. Further, we conclude the benchmarking principle and methodology on big data benchmarking from a recent open-source effort – BigDataBench. © Springer International Publishing Switzerland 2016.

关键词： Benchmarking

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Accelerating Iterative Big Data computing Through MPI

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Journal of computer Science & technology 2015年第2期30卷 283-294页

作者：梁帆鲁小亿 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China Department of Computer Science and Engineering The Ohio State University Columbus OH 43210-1277 U.S.A

Current popular systems, Hadoop and Spark, cannot achieve satisfied performance because of the inefficient overlapping of computation and communication when running iterative big data applications. The pipeline of computing, data movement, and data management plays a key role for current distributed data computing systems. In this paper, we first analyze the overhead of shuffle operation in Hadoop and Spark when running PageRank workload, and then propose an event-driven pipeline and in-memory shuffle design with better overlapping of computation and communication as DataMPI- Iteration, an MPI-based library, for iterative big data computing. Our performance evaluation shows DataMPI-Iteration can achieve 9X-21X speedup over Apache Hadoop, and 2X-3X speedup over Apache Spark for PageRank and K-means.

关键词： iterative computation DataMPI Spark Hadoop MapReduce

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