Many NoSQL (Not Only SQL) databases were proposed to store and query on a huge amount of data. Some of them like BigTable, PNUTS, and HBase, can be modeled as distributed ordered tables (DOTs). Many additional ind...
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Many NoSQL (Not Only SQL) databases were proposed to store and query on a huge amount of data. Some of them like BigTable, PNUTS, and HBase, can be modeled as distributed ordered tables (DOTs). Many additional indexing techniques have been presented to support queries on non-key columns for DOTs. However, there was no comprehensive analysis or comparison of these techniques, which brings troubles to users in selecting or proposing a proper indexing technique for a certain workload. This paper proposes a taxonomy based on six indexing issues to classify indexing techniques on DOTs and provides a comprehensive review of the state-of-the-art techniques. Based on the taxonomy, we propose a performance model named QSModel to estimate the query time and storage cost of these techniques and run experiments on a practical workload from Tencent to evaluate this model. The results show that the maximum error rates of the query time and storage cost are 24.2% and 9.8% respectively. Furthermore, we propose IndexComparator, an open source project that implements representative indexing techniques. Therefore, users can select the best-fit indexing technique based on both theoretical analysis and practical experiments.
Mining from simulation data of the golden model in hardware design verification is an effective solution to assertion *** the simulation data is inherently incomplete,it is necessary to evaluate the truth values of th...
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Mining from simulation data of the golden model in hardware design verification is an effective solution to assertion *** the simulation data is inherently incomplete,it is necessary to evaluate the truth values of the mined *** paper presents an approach to evaluating and constraining hardware assertions with absent scenarios.A Belief-fail Rate metric is proposed to predict the truth/falseness of generated *** considering both the occurrences of free variable assignments and the conflicts of absent scenarios,we use the metric to sort true assertions in higher ranking and false assertions in lower *** Belief-failRate guided assertion constraining method leverages the quality of generated *** experimental results show that the Belief-failRate framework performs better than the existing *** addition,the assertion evaluating and constraining procedure can find more assertions that cover new design functionality in comparison with the previous methods.
Due to the decreasing threshold voltages, shrinking feature size, as well as the exponential growth of on-chip transistors, modern processors are increasingly vulnerable to soft errors. However, traditional mechanisms...
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Due to the decreasing threshold voltages, shrinking feature size, as well as the exponential growth of on-chip transistors, modern processors are increasingly vulnerable to soft errors. However, traditional mechanisms of soft error mitigation take actions to deal with soft errors only after they have been detected. Instead of the passive responses, this paper proposes a novel mechanism which proactively prevents from the occurrence of soft errors via architecture elasticity. In the light of a predictive model, we adapt the processor architectures h01istically and dynamically. The predictive model provides the ability to quickly and accurately predict the simulation target across different program execution phases on any architecture configurations by leveraging an artificial neural network model. Experimental results on SPEC CPU 2000 benchmarks show that our method inherently reduces the soft error rate by 33.2% and improves the energy efficiency by 18.3% as compared with the static configuration processor.
Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-sca...
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Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs. Thre dimensional (3D) integration has been proposed to sustain Moore's law by incorporating through-silicon vias (TSVs) to integrate different circuit modules in the vertical direction, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-on- Chips (SoCs). Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. In addition, vertical interconnects, i.e., TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding pads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively. It is composed of two steps, i.e., scan chain allocation and functional input/output insertion, both of which can reduce TSV count significantly. Through extensive experimental evaluations, it is shown that reduce the number of test TSVs dramatically, i.e., as much as 26% in comparison with the intuitive method. the test wrapper chain structure designed by our method can 60.5% reductions in comparison with the random method and
Maximal multi-photon entangled states,known as NOON states,play an essential role in quantum *** the number of photons growing,NOON states are becoming increasingly powerful and advantageous for obtaining supersensiti...
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Maximal multi-photon entangled states,known as NOON states,play an essential role in quantum *** the number of photons growing,NOON states are becoming increasingly powerful and advantageous for obtaining supersensitive and super-resolved *** this paper,we propose a universal scheme for generating three-and four-photon path-entangled NOON states on a reconfigurable photonic chip via photons subtracted from pairs and detected by heralding *** method is postselection free,enabling phase supersensitive measurements and sensing at the Heisenberg *** NOON-state generator allows for integration of quantum light sources as well as practical and portable precision phase-related measurements.
In order to build a fault-tolerant network, heterogeneous facilities are arranged in the network to prevent homogeneous faults from causing serious damage. This paper uses edge-colored graph to investigate the feature...
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In order to build a fault-tolerant network, heterogeneous facilities are arranged in the network to prevent homogeneous faults from causing serious damage. This paper uses edge-colored graph to investigate the features of a network topology which is survivable after a set of homogeneous devices malfunction. We propose an approach to designing such networks under arbitrary parameters. We also show that the proposed approach can be used to optimize inter-router connections in network-on-chip to reduce the additional consum!otion of energy and time delay.
Side-channel analysis was introduced by Kocher et al.[1,2]which marked the outbreak of this new research field in the applied cryptography ***,many side-channel analysis methods have been published,for example,correla...
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Side-channel analysis was introduced by Kocher et al.[1,2]which marked the outbreak of this new research field in the applied cryptography ***,many side-channel analysis methods have been published,for example,correlation power analysis(CPA)[3],template attack[4],collision attack[5,6],mutual information analysis[7]
The poor energy proportionality of server is seen as the principal source for low energy efficiency of modern data centers. We find that different resource configurations of an application lead to similar performance,...
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The poor energy proportionality of server is seen as the principal source for low energy efficiency of modern data centers. We find that different resource configurations of an application lead to similar performance, but have distinct energy consumption. We call this phenomenon as "performance-equivalent resource configurations (PERC)", and its performance range is called equivalent region (ER). Based on PERC, one basic idea for improving energy efficiency is to select the most efficient configuration from PERC for each application. However, it cannot support every application to obtain optimal solution when thousands of applications are run simultaneously on resource-bounded servers. Here we propose a heuristic scheme, CPicker, based on genetic programming to improve energy efficiency of servers. To speed up convergence, CPicker initializes a high quality population by first choosing configurations from regions that have high energy variation. Experiments show that CPicker obtains above 17% energy efficiency improvement compared with the greedy approach, and less than 4% efficiency loss compared with the oracle case.
Benchmarking as yardsticks for system design and evaluation, has developed a long period and plays a pivotal role in many domains, such as database systems and high performance computing. Through prolonged and unremit...
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Current popular systems, Hadoop and Spark, cannot achieve satisfied performance because of the inefficient overlapping of computation and communication when running iterative big data applications. The pipeline of com...
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Current popular systems, Hadoop and Spark, cannot achieve satisfied performance because of the inefficient overlapping of computation and communication when running iterative big data applications. The pipeline of computing, data movement, and data management plays a key role for current distributed data computing systems. In this paper, we first analyze the overhead of shuffle operation in Hadoop and Spark when running PageRank workload, and then propose an event-driven pipeline and in-memory shuffle design with better overlapping of computation and communication as DataMPI- Iteration, an MPI-based library, for iterative big data computing. Our performance evaluation shows DataMPI-Iteration can achieve 9X-21X speedup over Apache Hadoop, and 2X-3X speedup over Apache Spark for PageRank and K-means.
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