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Cross-layer optimized placement and routing for FPGA soft error mitigation

Cross-layer optimized placement and routing for FPGA soft er...

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作者： Huang, Keheng Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

ISBN: (纸本)9783981080179

As the feature size of FPGA shrinks to nanometers, soft errors increasingly become an important concern for SRAM-based FPGAs. Without consideration of the application level impact, existing reliability-oriented placement and routing approaches analyze soft error rate (SER) only at the physical level, consequently completing the design with suboptimal soft error mitigation. Our analysis shows that the statistical variation of the application level factor is significant. Hence in this work, we first propose a cube-based analysis to efficiently and accurately evaluate the application level factor. And then we propose a cross-layer optimized placement and routing algorithm to reduce the SER by incorporating the application level and the physical level factor together. Experimental results show that, the average difference of the application level factor between our cube-based method and Monte Carlo golden simulation is less than 0.01. Moreover, compared with the baseline VPR placement and routing technique, the cross-layer optimized placement and routing algorithm can reduce the SER by 14% with no area and performance overhead. © 2011 EDAA.

关键词： Field programmable gate arrays (FPGA)

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On diagnosis of multiple faults using compacted responses

On diagnosis of multiple faults using compacted responses

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作者： Ye, Jing Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

ISBN: (纸本)9783981080179

With the exponential growth in the number of transistors, not only test data volume and test application time may increase, but also multiple faults may exist in one chip. Test compaction has been a de-facto design-for-testability technique to reduce the test cost. However, the compacted test responses make multiple-fault diagnosis rather difficult. When there is no space compactor, the most likely suspect fault is considered producing the failing responses most similar to the failing responses observed from the automatic test equipment. But when compactor exists, those suspect faults may no longer have the same high possibility of being the actual faults. To address this problem, we introduce a novel metric explanation necessity. By using both of the new metric and the traditional metric explanation capability, we evaluate the possibility of a suspect fault to be the actual fault. For ISCAS'89 and ITC'99 benchmark circuits equipped with extreme space compactors, experimental results show that 98.8% of the top-ranked suspect faults hit the actual faults, outperforming a previous work by 11.3%. © 2011 EDAA.

关键词： Design for testability

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A cost-effective substantial-impact-filter based method to tolerate voltage emergencies

A cost-effective substantial-impact-filter based method to t...

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作者： Pan, Songjun Hu, Yu Hu, Xing Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

ISBN: (纸本)9783981080179

Supply voltage fluctuation caused by inductive noises has become a critical problem in microprocessor design. A voltage emergency occurs when supply voltage variation exceeds the acceptable voltage margin, jeopardizing the microprocessor reliability. Existing techniques assume all voltage emergencies would definitely lead to incorrect program execution and prudently activate rollbacks or flushes to recover, and consequently incur high performance overhead. We observe that not all voltage emergencies result in external visible errors, which can be exploited to avoid unnecessary protection. In this paper, we propose a substantial-impact-filter based method to tolerate voltage emergencies, including three key techniques: 1) Analyze the architecture-level masking of voltage emergencies during program execution;2) Propose a metric intermittent vulnerability factor for intermittent timing faults (IV F itf) to quantitatively estimate the vulnerability of microprocessor structures (load/store queue and register file) to voltage emergencies;3) Propose a substantial-impact-filter based method to handle voltage emergencies. Experimental results demonstrate our approach gains back nearly 57% of the performance loss compared with the once-occur-then-rollback approach. © 2011 EDAA.

关键词： Cost effectiveness

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A Case Study: Low Power Design-for-Testability Features of a Multi-core Processor Godson-T

A Case Study: Low Power Design-for-Testability Features of a...

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2011 2nd International Conference on Advanced Measurement and Test (AMT 2011)

作者： Da Wang Dongrui Fan Yu Hu Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

This paper describes the low power test challenges and features of a multi-core processor, Godson-T, which contains 16 identical coresSince the silicon design technology scales to ultra deep submicron and even nanometers, the complexity and cost of testing is growing up, and the test power of such designs is extremely curious, especially for multicore processorsIn this paper, we use the modular design methodology and scaleable design-for-testability(DFT) structure to achieve low test power, at the same time, an improved test pattern generation method is studied to reduce test power further moreThe experimental results from the real chip show that the test power and test time are well balanced while achieving acceptable test coverage and cost.

关键词： design-for-testability(DFT),multi-core processor,very large scale integration(VLSI),power reduction,pattern filling,multi-capture

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Processes scheduling on heterogeneous multi-core architecture with hardware support

Processes scheduling on heterogeneous multi-core architectur...

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IEEE International Conference on Networking, architecture and Storage

作者： Hao, Shouqing Liu, Qi Zhang, Longbing Wang, Jian Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences China Loongson Technology Corporation Limited China

ISBN: (纸本)9780769545097

Heterogeneous Chip Multi-Processors (heter-CMP) provide suitable resources to various applications and could get more benefits on performance than homogeneous CMP. To fully develop the performance of the heter-CMP system, the applications should be scheduled to the proper cores by the scheduler of the operating system according to their behaviours. Besides, the last level cache (LLC) miss rate is often used as the metric to identify the application features. However, the LLC miss rate could not reflect the application behaviours accurately since the memory access delay, the most important application character is related to patterns of the memory access and many other issues. To improve the accuracy of scheduling on the heter-CMP system, this paper supplies performance counters for the LLC miss penalty to monitor application behaviours. Based on that, the latency-aware scheduling algorithm for asymmetry chip multi-processors (LA-ACMP) is proposed and implemented. Those hardware supports are implemented on the Godson-3 multi-core RTL and simulator and the LA-ACMP algorithm is integrated to the Linux kernel. The performance evaluation on those platforms shows that the LA-ACMP algorithm with LLC miss penalty outperforms the algorithm with LLC miss rate about 32.4%, and outperforms the original schedule algorithm about 18.4%. © 2011 IEEE.

关键词： Scheduling algorithms

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An efficient shared memory based virtual communication system for embedded SMP cluster

An efficient shared memory based virtual communication syste...

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IEEE International Conference on Networking, architecture and Storage

作者： Yin, Wenxuan Gao, Xiang Zhu, Xiaojing Guo, Deyuan Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Loongson Technology Corporation Limited Beijing China Institute of Microelectronics Tsinghua University Beijing China

ISBN: (纸本)9780769545097

With the prevalence of multi-core processors, it is a trend that the embedded cluster deploys SMP nodes to gain more computing power. As a crucial issue, the MPI interprocess communication has been suffering the contradiction between high performance and embedded constraints. Moreover, there is a big performance gap between intra- and inter-node communication for different infrastructures. In this paper, we design a virtual communication system called SMVN, which extends the shared memory mechanism typically used in intra-node case into the inter-node case. The SMVN utilizes the HT inter-chip interconnect interface in Godson-3A SMP nodes to build a mesh topology. It is Ethernet compatible by simulating bottom layers of TCP/IP protocol. With the design, the node interconnection can get rid of NICs, cables and switches. Furthermore, we exploit the zero-copy scheme and other optimizations to improve the performance. We port the MPICH2 library by socket channel and formulate its process allocation. The MPI latency and bandwidth tests show that the performance difference between two levels is small. The inter-node bandwidth is 27.3MB/s, which is more than twice the theoretical peak value of 100Mb Ethernet and reaches 84% of the intra-node performance. © 2011 IEEE.

关键词： Bandwidth

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Building algorithmically nonstop fault tolerant MPI programs

Building algorithmically nonstop fault tolerant MPI programs

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International Conference on High Performance computing

作者： Rui Wang Erlin Yao Mingyu Chen Guangming Tan Pavan Balaji Darius Buntinas State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Mathematics and Computer Science Argonne National Laboratory USA

With the growing scale of high-performance computing (HPC) systems, today and more so tomorrow, faults are a norm rather than an exception. HPC applications typically tolerate fail-stop failures under the stop-and-wait scheme, where even if only one processor fails, the whole system has to stop and wait for the recovery of the corrupted data. It is now a more-or-less accepted fact that the stop-and-wait scheme will not scale to the next generation of HPC systems. Inspired by the previous stop-and-wait algorithm-based fault tolerance (ABFT) recovery technique, we propose in this paper a nonstop fault tolerance scheme at the application level and describe its implementation. When failure occurs during the execution of applications, we do not stop to wait for the recovery of the corrupted node; instead, we replace it with the corresponding redundant node and continue the execution. At the end of execution, the correct solution can be recovered algorithmically at a very low cost. In order to implement the scheme, some new fault-tolerant features of the Message Passing Interface (MPI) have been investigated and utilized in the MPICH implementation of MPI. We also describe a case study using High Performance Linpack (HPL) with these new features and evaluate the performance of both our new scheme and ABFT recovery. Experimental results show the advantage of our new scheme over ABFT recovery even in a small scale.

关键词： Fault tolerant systems Encoding Redundancy Checkpointing Matrix decomposition Libraries

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Empirical design bugs prediction for verification

Empirical design bugs prediction for verification

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作者： Guo, Qi Chen, Tianshi Shen, Haihua Chen, Yunji Wu, Yue Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Beijing 100049 China Loongson Technologies Corporation Limited Beijing 100190 China

ISBN: (纸本)9783981080179

Coverage model is the main technique to evaluate the thoroughness of dynamic verification of a Design-under-Verification (DUV). However, rather than achieving a high coverage, the essential purpose of verification is to expose as many bugs as possible. In this paper, we propose a novel verification methodology that leverages the early bug prediction of a DUV to guide and assess related verification process. To be specific, this methodology utilizes predictive models built upon artificial neural networks (ANNs), which is capable of modeling the relationship between the high-level attributes of a design and its associated bug information. To evaluate the performance of constructed predictive model, we conduct experiments on some open source projects. Moreover, we demonstrate the usability and effectiveness of our proposed methodology via elaborating experiences from our industrial practices. Finally, discussions on the application of our methodology are presented. © 2011 EDAA.

关键词： Neural networks

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Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs

Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-...

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Asian Test Symposium (ATS)

作者： Keheng Huang Yu Hu Xiaowei Li Gengxin Hua Hongjin Liu Bo Liu State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Beijing Institute of Control Engineering China

As the feature size of FPGA shrinks to nanometers, SRAM-based FPGAs are more vulnerable to soft errors. During logic synthesis, reliability of the design can be improved by introducing logic masking effect. In this work, we observe that there are a lot of not-fully occupied look-up tables (LUTs) after logic synthesis. Hence, we propose a functional equivalent class based soft error mitigation scheme to exploit free LUT entries in the circuit. The proposed technique replaces not fully-occupied LUTs with corresponding functional equivalent classes, which can improve the reliability while preserve the functionality of the design. Experimental results show that, compared with the baseline ABC mapper, the proposed technique can reduce the soft error rate by 21%, and the critical-path delay increase is only 4.25%.

关键词： Table lookup Circuit faults Forward error correction Field programmable gate arrays Vectors Reliability engineering

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Optimizing MPI alltoall communication of large messages in multicore clusters

Optimizing MPI alltoall communication of large messages in m...

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2011 12th International Conference on Parallel and Distributed computing, Applications and Technologies, PDCAT 2011

作者： Li, Qiang Huo, Zhigang Sun, Ninghui Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Chinese Academy of Sciences Graduate University Beijing 100049 China

ISBN: (纸本)9780769545646

MPI Alltoall communication is widely used in many high performance computing (HPC) applications. In Alltoall communication, each process sends a distinct message to all other participating processes. In multicore clusters, processes within a node simultaneously contend for the same network resource of the node in Alltoall communication. However, many small synchronization messages are required in Alltoall communication of large messages. With the contention, their latency is orders of magnitude larger than that without contention. As a result, the synchronization overhead is significantly increased and accounts for a large proportion to the whole latency of Alltoall communication. In this paper, we analyse the considerable overhead of synchronization messages. Base on the analysis, an optimization is presented to reduce the number of synchronization messages from 3N to 2√N. Evaluations on a 240-core cluster show that the performance is improved by almost constant ratio, which is mainly determined by message size and independent of system scale. The performance of Alltoall communication is improved by 25% for 32K and 64K bytes messages. For FFT application, performance is improved by 20%. © 2011 IEEE.

关键词： Synchronization

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