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International Conference on Networking, architecture, and Storage (NAS)

作者： Wenxuan Yin Xiang Gao Xiaojing Zhu Deyuan Guo Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Institute of Microelectronics Tsinghua University Beijing China

With the prevalence of multi-core processors, it is a trend that the embedded cluster deploys SMP nodes to gain more computing power. As a crucial issue, the MPI inter-process communication has been suffering the contradiction between high performance and embedded constraints. Moreover, there is a big performance gap between intra- and inter-node communication for different infrastructures. In this paper, we design a virtual communication system called SMVN, which extends the shared memory mechanism typically used in intra-node case into the inter-node case. The SMVN utilizes the HT inter-chip interconnect interface in Godson-3A SMP nodes to build a mesh topology. It is Ethernet compatible by simulating bottom layers of TCP/IP protocol. With the design, the node interconnection can get rid of NICs, cables and switches. Furthermore, we exploit the zero-copy scheme and other optimizations to improve the performance. We port the MPICH2 library by socket channel and formulate its process allocation. The MPI latency and bandwidth tests show that the performance difference between two levels is small. The inter-node bandwidth is 27.3 MB/s, which is more than twice the theoretical peak value of 100 Mb Ethernet and reaches 84% of the intra-node performance.

关键词： Program processors IP networks Protocols computer architecture Bandwidth Resource management Synchronization

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Dynamic Resource Allocation Based on User experience in Virtualized Servers

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Procedia Engineering 2011年 15卷 3780-3784页

作者： Wei Zhang Jiajun Liu Ying Song Mingfa Zhu Limin Xiao Yuzhong Sun Li Ruan State Key Laboratory of Software Development Environment Beijing 100191 China School of Computer Science and Engineering Beihang University Beijing 100191 China Key Laboratory of Computer System and Architecture Chinese Academy of SciencesBeijing Institute of Computing Technology Chinese Academy of Sciences Beijing China

Web workloads are known to vary dynamically with time which poses a challenge to resource allocation among the applications. In this paper, we argue that the existing dynamic resource allocation based on resource utilization has some drawbacks in virtualized servers. Dynamic resource allocation directly based on real-time user experience is more reasonable and also has practical significance. To address the problem, we propose a system architecture that combines real time measurements and analysis of user experience for resource allocation. We evaluate our proposal using Webbench. The experiment results show that these techniques can judiciously allocate system resources.

关键词： resource allocation virtualized servers user experience

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Context-specific miRNA regulation network predicts cancer prognosis

Context-specific miRNA regulation network predicts cancer pr...

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5th IEEE International Conference on Systems Biology, ISB 2011

作者： Zhou, Xionghui Liu, Juan Liu, Changning Rayner, Simon Liang, Fengji Ju, Jingfang Li, Yinghui Chen, Shanguang Xiong, Jianghui School of Computer Science Wuhan University Wuhan China Beijing China Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Beijing China State Key Laboratory of Virology Wuhan Institute of Virology Chinese Academy of Sciences Wuhan China Department of Pathology Stony Brook University Medical Center NY United States

ISBN: (纸本)9781457716669

MicroRNAs can regulate hundreds of target genes and play a pivotal role in a broad range of biological process. However, relatively little is known about how these highly connected miRNAs-target networks are remodelled in the context of various diseases. Here we examine the dynamic alteration of context-specific miRNA regulation to determine whether modified microRNAs regulation on specific biological processes is a useful information source for predicting cancer prognosis. A new concept, Context-specific miRNA activity (CoMi activity) is introduced to describe the statistical difference between the expression level of a miRNA's target genes and non-targets genes within a given gene set (context). The microarray gene expression profile of brain tumors from 356 patients (The Cancer Genome Atlas dataset) was converted into a CoMi activity pattern, and showed significant positive correlation with the corresponding miRNA expression pattern. In a breast cancer cohort, the differential CoMi activity between good prognosis (longer survival) vs. bad prognosis patients forms a scale-free network, which highlighted a group of important cancer-related microRNAs and GO terms, e.g. hsa-miR-34a and 'cell adhesion'. Then two breast cancer cohorts were used in outcome prediction in an independent test. Using a popular T-test feature selection method and a support vector machine (SVM) classifier with 10-fold cross-validation, the CoMi activity feature achieves an area under curve (AUC) of 0.7155, better than the AUC value of 0.6339 for feature selection based on mRNA expression. In an independent test, CoMi feature selection achieved an AUC of 0.6874. Survival analysis also shows signatures defined by CoMi activity was predictive of survival and superior to mRNAs signatures. In short, we have demonstrated the first interrogation of dynamic remodeling of context specific miRNAs regulation networks in cancer. The altered microRNAs regulation on specific contexts could be used to predi

关键词： Diseases

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Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors

Transparent dynamic binding with fault-tolerant cache cohere...

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International Conference on Dependable Systems and Networks (DSN)

作者： Shuchang Shan Yu Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level fault-tolerant approaches bind two cores to implement redundant execution and error detection. However, along with more cores integrated into one chip, existing static and dynamic binding schemes suffer from the scalability problem when considering the violation effects caused by external write operations. In this paper, we present a transparent dynamic binding (TDB) mechanism to address the issue. Learning from static binding schemes, we involve the private caches to hold identical data blocks, thus we reduce the global masters-lave consistency maintenance to the scale of the private caches. With our fault-tolerant cache coherence protocol, TDB satisfies the objective of private cache consistency, therefore provides excellent scalability and flexibility. Experimental results show that, for a set of parallel workloads, the overall performance of our TDB scheme is very close to that of baseline fault-tolerant systems, outperforming dynamic core coupling by 9.2%, 10.4%, 18% and 37.1% when considering 4, 8, 16 and 32 cores respectively.

关键词： Master-slave Fault tolerance Fault tolerant systems Coherence System-on-a-chip Pipelines

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Theoretical treatment of sink scheduling problem in wireless sensor networks

Theoretical treatment of sink scheduling problem in wireless...

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2011 IEEE Conference on computer Communications Workshops, INFOCOM WKSHPS 2011

作者： Gu, Yu Ji, Yusheng Li, Jie Zhao, Baohua Information Systems Architecture Science Research Division National Institute of Informatics Tokyo Japan State Key Laboratory of Networking and Switching Technology Beijing 100876 China School of Computer Science Univ. of Science and Technology of China Hefei Anhui 230027 China Department of Computer Science University of Tsukuba Ibaraki 305-8573 Japan

ISBN: (纸本)9781457702488

Sink Scheduling, in the form of scheduling multiple sinks among sink sites to leverage traffic burden, is an effective mechanism for the energy-efficiency of wireless sensor networks (WSNs). Due to the inherent difficulty (NP-hard in general), existing works on this topic mainly focus on heuristic/greedy algorithms and theoretic results remain unknown. In this paper, we fill in the research blank with two algorithms. The first one is based on the Column Generation (CG). It decomposes the original problem into two sub problems and solve them iteratively to approach the optimal solution. However, due to its high computational complexity, this algorithm is only suitable for small scale networks. The other one is a polynomial-time algorithm based on relaxation techniques to obtain an upperbound, which can serve as a performance benchmark for other algorithms on this problem. Through comprehensive simulations, we evaluate the efficiency of proposed algorithms. © 2011 IEEE.

关键词： Wireless sensor networks

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PADS: A Pattern-Driven Stencil Compiler-Based Tool for Reuse of Optimizations on GPGPUs

PADS: A Pattern-Driven Stencil Compiler-Based Tool for Reuse...

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International Conference on Parallel and Distributed Systems (ICPADS)

作者： Dongni Han Shixiong Xu Li Chen Lei Huang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Computer Science Department Prairie View A&M University USA

Stencil computations are core of wide range of scientific and engineering applications. A lot of efforts have been put into improving efficiency of stencil calculations on different platforms, but unfortunately it is not easy to reuse. In this paper we present a PAttern-Driven Stencil compiler-based tool and a simple tuning system to reuse those well optimized methods and codes. We also suggest extensions to OpenMP, depicting high-level data structures in order to facilitate recognition of various stencil computation patterns. The PADS allows programmers to rewrite kernel of stencils or reuse source-to-source translator outputs as optimized stencil template codes with related tuning parameters, In addition, PADS consists of a OpenMP to CUDA translator and code generator using optimized template codes. It also obtains architecture-specific parameters to tune stencils across different GPU platforms. To demonstrate our system flexibility and performance portability, we illustrate four different stencil computations, Laplacian operator with Jacobi iterative method, divergence operator, 3 dimension 25 point stencil and a 2D heat equation using ADI method with periodic boundary conditions. PADS succeeds in generating all these four stencil codes using different optimization strategies and delivers a promising performance improvement.

关键词： Pattern matching Kernel Tuning Libraries Optimization Generators

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Empirical design bugs prediction for verification

Empirical design bugs prediction for verification

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Design, Automation and Test in Europe Conference and Exhibition

作者： Qi Guo Tianshi Chen Haihua Shen Yunji Chen Yue Wu Weiwu Hu Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Coverage model is the main technique to evaluate the thoroughness of dynamic verification of a Design-under-Verification (DUV). However, rather than achieving a high coverage, the essential purpose of verification is to expose as many bugs as possible. In this paper, we propose a novel verification methodology that leverages the early bug prediction of a DUV to guide and assess related verification process. To be specific, this methodology utilizes predictive models built upon artificial neural networks (ANNs), which is capable of modeling the relationship between the high-level attributes of a design and its associated bug information. To evaluate the performance of constructed predictive model, we conduct experiments on some open source projects. Moreover, we demonstrate the usability and effectiveness of our proposed methodology via elaborating experiences from our industrial practices. Finally, discussions on the application of our methodology are presented.

关键词： computer bugs Predictive models Complexity theory Measurement Training data Training Correlation

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Cross-layer optimized placement and routing for FPGA soft error mitigation

Cross-layer optimized placement and routing for FPGA soft er...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Keheng Huang Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

As the feature size of FPGA shrinks to nanometers, soft errors increasingly become an important concern for SRAM-based FPGAs. Without consideration of the application level impact, existing reliability-oriented placement and routing approaches analyze soft error rate (SER) only at the physical level, consequently completing the design with suboptimal soft error mitigation. Our analysis shows that the statistical variation of the application level factor is significant. Hence in this work, we first propose a cube-based analysis to efficiently and accurately evaluate the application level factor. And then we propose a cross-layer optimized placement and routing algorithm to reduce the SER by incorporating the application level and the physical level factor together. Experimental results show that, the average difference of the application level factor between our cube-based method and Monte Carlo golden simulation is less than 0.01. Moreover, compared with the baseline VPR placement and routing technique, the cross-layer optimized placement and routing algorithm can reduce the SER by 14% with no area and performance overhead.

关键词： Routing Wires Circuit faults Field programmable gate arrays Monte Carlo methods Algorithm design and analysis Accuracy

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A SAT-Based Pattern Generation Method for Diagnosis Multiple Scan Chain Faults

A SAT-Based Pattern Generation Method for Diagnosis Multiple...

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2011 2nd International Conference on Advanced Measurement and Test (AMT 2011)

作者： Fei Wang Da Wang Haigang Yang System on Programmable Chip Research Department Institute of Electronics Chinese Academy of Sciences Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

Scan chain design is a widely used design-for-testability(DFT) technique to improve test and diagnosis qualityHowever, failures on scan chain itself account for up to 30% of chip failuresTo diagnose root causes of scan chain failures in a short period is vital to failure analysis process and yield improvementsAs the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysisIn this paper, a SAT-based technique is proposed to generate patterns to diagnose scan chain faultsThe proposed work can efficiently generate high quality diagnostic patterns to achieve high diagnosis resolutionMoreover, the computation overhead of proving equivalent faults is reducedExperimental results on ISCAS'89 benchmark circuits show that the proposed method can reduce the number of diagnostic patterns while achieving high diagnosis resolution.

关键词： scan chain,testing,diagnosis,boolean satisfiability(SAT),very large scale integration

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A fine-grained component-level power measurement method

A fine-grained component-level power measurement method

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International Green computing Conference

作者： Zehan Cui Yan Zhu Yungang Bao Mingyu Chen Chinese Academy and Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

ISBN: (纸本)9781457712227

The ever growing energy consumption of computer systems have become a more and more serious problem in the past few years. Power profiling is a fundamental way for us to better understand where, when and how energy is consumed. This paper presents a direct measurement method to measure the power of main computer components with fine time granularity. To achieve this goal, only small amount of extra hardware are employed. An approach to synchronize power dissipation with program phases has also been proposed in this paper. Based on the preliminary version of our tools, we measure the power of CPU, memory and disk when running SPEC CPU2006 benchmarks, and prove that measurement with fine time granularity is essential. The phenomenon we observe from memory power may be served as a guide for memory management or architecture design towards energy efficiency.

关键词： Power measurement Current measurement Wires Voltage measurement Connectors Central Processing Unit Time measurement

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