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International Symposium on VLSI Design, Automation and Test

作者： Huawei Li Dawen Xu Kwang-Ting Cheng Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Department of Electrical and Computer Engineering University of California Santa Barbara CA USA

GPUs have recently been explored as a new general-purpose computing platform, which are suitable for the acceleration of compute-intensive EDA applications. In this paper we describe a GPU-based one- to n-detection fault simulator for both stuck-at and transition faults, which demonstrates a 20X speedup over a commercial CPU-based fault simulator. We further show new fault-simulation-based test selection applications enabled by this accelerated fault simulation. Our results demonstrate that the tests selected from the applications achieve higher fault coverages for 1-to-n detections with steeper fault coverage curves, as well as a better delay test quality, in comparison with tests deterministically generated by commercial ATPG tools.

关键词： Circuit faults Graphics processing unit Instruction sets Delay Integrated circuit modeling Logic gates Computational modeling

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Optimizing Web Browser on Many-Core architectures

Optimizing Web Browser on Many-Core Architectures

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IEEE International Conference on Parallel and Distributed computing, Applications and Technologies (PDCAT)

作者： Lingjun Fan Weisong Shi Shibin Tang Chenggang Yan Dongrui Fan Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Wayne State University Detroit USA

As more and more Web applications emerging on sever end today, the Web browser on client end has become a host of a variety of applications other than just rendering static Web pages. This leads to more and more performance requirements of a Web browser, for which user experience is very important. This situation may become more urgency when on handheld devices. Some efforts like redesign a new Web browser have been made to overcome this problem. In this paper, we address this issue by optimizing the main processes of the Web browser on a state-of-the-art 64-core architecture, Godson-T, which was developed at Chinese Academy of Sciences, as multi-/many-core architecture to be the mainstream processor in the upcoming years. We start a new core to process a new tab when facing up to intensive URL requests, and we use scratch-pad memory (SPM) of each core as a local buffer to store the HTML source data to be processed to reduce off-chip memory access and exploit more data locality, otherwise, we use DTA to transfer HTML data for backup. Experiments conducted on the cycle-accurate simulator show that, starting each tab process by a new core could obtain 5.7% to 50% speedup with different number of cores used to process corresponding URL requests, with on-chip scratchpad memory of each core used to store the HTML data, more speedup could be achieved when number of cores increase. Also, as Data Transfer Agent (DTA) used to transfer the HTML data, the backup of HTML data can get 2X to 5X speedups according to different data amount.

关键词： Browsers HTML Web pages Layout Multicore processing System-on-a-chip

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An ultra-fast hybrid simulation framework for ASIP

An ultra-fast hybrid simulation framework for ASIP

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Ji Qiu Xiang Gao Yifei Jiang Xu Xiao Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences (CAS) Beijing China Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign Urbana IL USA

ISS (Instruction Set Simulator) plays an important role in pre-silicon software development for ASIP. However, the speed of traditional simulation is too slow to effectively support full-scale software development. In this paper, we propose a hybrid simulation framework which further improves the previous simulation methods by aggressively utilizing the host machine resources. The utilization is achieved by categorizing instructions of ASIP application into two types, namely custom and basic instructions, via binary instrumentation. Then in a way of hybrid simulation, only custom instructions are simulated on the ISS and basic instructions are executed fast and natively on the host machine. We implement this framework for an industrial ASIP to validate our approach. Experimental results show that when the implemented ISS, namely GS-Sim, is applied to practical multimedia decoders, an average simulation speed up to 1058.5MIPS can be achieved, which is 34.7 times of the state-of-art dynamic binary translation simulator and is the fastest to the best of our knowledge.

关键词： Instruments Context Programming Decoding Switches Prototypes Context modeling

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Optimizing MPI Alltoall Communication of Large Messages in Multicore Clusters

Optimizing MPI Alltoall Communication of Large Messages in M...

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IEEE International Conference on Parallel and Distributed computing, Applications and Technologies (PDCAT)

作者： Qiang Li Zhigang Huo Ninghui Sun Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing CN

MPI All to all communication is widely used in many high performance computing (HPC) applications. In All to all communication, each process sends a distinct message to all other participating processes. In multicore clusters, processes within a node simultaneously contend for the same network resource of the node in All to all communication. However, many small synchronization messages are required in All to all communication of large messages. With the contention, their latency is orders of magnitude larger than that without contention. As a result, the synchronization overhead is significantly increased and accounts for a large proportion to the whole latency of All to all communication. In this paper, we analyse the considerable overhead of synchronization messages. Base on the analysis, an optimization is presented to reduce the number of synchronization messages from 3N to 2¡ÌN. Evaluations on a 240-core cluster show that the performance is improved by almost constant ratio, which is mainly determined by message size and independent of system scale. The performance of All to all communication is improved by 25% for 32K and 64K bytes messages. For FFT application, performance is improved by 20%.

关键词： Synchronization Protocols Multicore processing Receivers Bandwidth Program processors Benchmark testing

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Provably secure role-based encryption with revocation mechanism

Provably secure role-based encryption with revocation mechan...

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作者： Zhu, Yan Hu, Hong-Xin Ahn, Gail-Joon Wang, Huai-Xi Wang, Shan-Biao Institute of Computer Science and Technology Peking University Beijing 100871 China Beijing Key Laboratory of Internet Security Technology Peking University Beijing 100871 China School of Computing Informatics and Decision Systems Engineering Arizona State University Tempe AZ 85287 United States 4School of Mathematical Sciences Peking University Beijing 100871 China

Role-Based Encryption (RBE) realizes access control mechanisms over encrypted data according to the widely adopted hierarchical RBAC model. In this paper, we present a practical RBE scheme with revocation mechanism based on partial-order key hierarchy with respect to the public key infrastructure, in which each user is assigned with a unique private-key to support user identification, and each role corresponds to a public group-key that is used to encrypt data. Based on this key hierarchy structure, our RBE scheme allows a sender to directly specify a role for encrypting data, which can be decrypted by all senior roles, as well as to revoke any subgroup of users and roles. We give a full proof of security of our scheme against hierarchical collusion attacks. In contrast to the existing solutions for encrypted file systems, our scheme not only supports dynamic joining and revoking users, but also has shorter ciphertexts and constant-size decryption keys. © 2011 Springer Science+Business Media, LLC & Science Press, China.

关键词： Access control

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A cost-effective substantial-impact-filter based method to tolerate voltage emergencies

A cost-effective substantial-impact-filter based method to t...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Songjun Pan Yu Hu Xing Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

Supply voltage fluctuation caused by inductive noises has become a critical problem in microprocessor design. A voltage emergency occurs when supply voltage variation exceeds the acceptable voltage margin, jeopardizing the microprocessor reliability. Existing techniques assume all voltage emergencies would definitely lead to incorrect program execution and prudently activate rollbacks or flushes to recover, and consequently incur high performance overhead. We observe that not all voltage emergencies result in external visible errors, which can be exploited to avoid unnecessary protection. In this paper, we propose a substantial-impact-filter based method to tolerate voltage emergencies, including three key techniques: 1) Analyze the architecture-level masking of voltage emergencies during program execution; 2) Propose a metric intermittent vulnerability factor for intermittent timing faults (IV F itf ) to quantitatively estimate the vulnerability of microprocessor structures (load/store queue and register file) to voltage emergencies; 3) Propose a substantial-impact-filter based method to handle voltage emergencies. Experimental results demonstrate our approach gains back nearly 57% of the performance loss compared with the once-occur-then-rollback approach.

关键词： Microprocessors Delay computer architecture Computational modeling Sensors Benchmark testing

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基于漏电变化表征的参数偏差在线预测方法

基于漏电变化表征的参数偏差在线预测方法

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第七届中国测试学术会议

作者： Jin Song 靳松 Han Yinhe 韩银和 Xu Qiang 徐强 Department of Electronic and Communication Engineering School of Electrical and Electronic Engineer 华北电力大学电气与电子工程学院电子与通信工程系保定071003 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of 中国科学院计算技术研究所计算机体系结构国家重点实验室北京100190 CUhk REliable Computing Laboratory(CURE) Department of Computer Science&Engineering The Chinese Un 香港中文大学计算机科学与工程系

负偏置温度不稳定(NBTI)引发的动态参数偏差给集成电路的生命期可靠性带来严重威胁。已有的方法主要通过设计片上检测电路实时监测关键通路的时延偏差来阻止NBTI导致的电路失效。然而，不断恶化的静、动参数偏差，不断增加的设计复杂度... 详细信息

负偏置温度不稳定(NBTI)引发的动态参数偏差给集成电路的生命期可靠性带来严重威胁。已有的方法主要通过设计片上检测电路实时监测关键通路的时延偏差来阻止NBTI导致的电路失效。然而，不断恶化的静、动参数偏差，不断增加的设计复杂度以及片上检测电路所引入的面积开销会影响上述方法的应用效果。为了弥补已有方法的不足，本文提出以测量到的电路漏电变化为表征，预测NBTI导致的电路时延偏差。首先，通过施加一组测量向量得到的电路漏电变化量被联立成一个方程组;求解方程组后可以得到关键通路上关键门的漏电变化量。随后，根据描述漏电变化与时延偏差相关性的分析表达式来预测任意关键通路的时延偏差。提出的方法对电路工作过程中的实时噪声免疫，且可以通过增加漏电测量时间抵消参数偏差对预测结果的影响。实验结果表明，提出的方法能够以可接受的精度损失有效地预测NBTI导致的电路时延偏差。

关键词：纳米集成电路负偏置温度不稳定性漏电变化时延监测

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Estimate-Piloted Regularization and Fast ALS Algorithm for Collaborative Filtering

Estimate-Piloted Regularization and Fast ALS Algorithm for C...

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2011 International Conference on Future computer Science and Education（ICFCSE 2011）

作者： Zhenyue Zhang Keke Zhao Hongyuan Zha Guirong Xue Department of Mathematics State Key Laboratory of CAD&CGZhejiang University College of Computing Georgia Institute of Technology Department of Computer Science Shanghai Jiao Tong University

Regularized Low-rank approximation with missing data is an effective approach for Collaborative Filtering since it generates high quality rating predictions for recommender systems. Alternative LS(ALS) method is one of the commonly used algorithms for the CF problem. However, ALS did not work very well in some applications, due to the over-fitting to observations. This paper proposes a novel estimate-piloted regularization that uses a pre-estimate of the unobserved entries and uses the approximation errors to the pre-estimates as a regularize term. This new regularization can reduce the risk of over-fitting and improve the approximation accuracy of *** also proposed a fast implementation of the modified ALS method, which is also very suitable for parallel computing. The proposed algorithm PALS has higher accuracy than ALS for original model in three real-world data sets.

关键词： lowrank-matrix completion collaborative filtering regularization technique alternate least squares

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Dynamic register promotion of stack variables 11

Dynamic register promotion of stack variables

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International Symposium on Code Generation and Optimization (CGO)

作者： Jianjun Li Chenggang Wu Wei-Chung Hsu Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Deparunent of Computer Science National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)9781612843568

Dynamic Binary Translation (DBT) has been widely used in various applications. Although new architectures and micro-architectures often create performance opportunities for programmers and compilers, such performance opportunities may not be exploited by legacy executables. For example, the additional general-purpose and XMM registers in the Intel64 architecture do not benefit the IA-32 binaries. In this paper, we designed and developed a DBT system to dynamically promote stack variables in the source binaries to the additional registers of the target architecture. One of the most challenging problems is how to deal with the possible but rare memory aliases between promoted stack variables and other implicit memory references. We devised a runtime alias detection approach based on the page protection mechanism in Linux and a novel stack switching method to catch memory aliases at run-time. This approach is much less expensive than traditional approaches like inserting address checking instructions. On an Intel64 platform, our DBT system with speculative stack variable promotion has sped up several SPEC CPU2006 benchmarks in IA-32 code, with the largest performance gain over 45%.

关键词： Registers Optimization Switches computer architecture Benchmark testing Runtime Program processors

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Trainbow: a new trusted virtual machine based platform

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中国高等学校学术文摘·计算机科学 2010年第1期4卷 47-64页

作者： Yuzhong SUN Yongbing HUANG Yunwei GAO Haifeng FANG Ying SONG Lei DU Kai ZHANG Hongyong ZANG Yaqiong LI Yajun YANG Ran AO Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Department of Computer Science and Technology Xi'an Jiaotong University Xi'an 710049China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China

Currently, with the evolution of virtualization technology, cloud computing mode has become more and more popular. However, people still concern the issues of the runtime integrity and data security of cloud computing platform, as well as the service efficiency on such computing platform. At the same time, according to our knowledge, the design theory of the trusted virtual computing environment and its core system software for such network-based computing platform is at the exploratory stage. In this paper, we believe that efficiency and isolation are the two key proprieties of the trusted virtual computing environment. To guarantee these two proprieties, based on the design principle of splitting, customizing, reconstructing, and isolation-based enhancing to the platform, we introduce TRainbow, a novel trusted virtual computing platform developing by our research *** the two creative mechanisms, that is, capacity flowing amongst VMs and VM-based kernel reconstructing, TRainbow provides great improvements (up to 42%) in service performance and isolated reliable computing environment for Internet-oriented, large-scale, concurrent services.

关键词： computing platform virtual machine capacity service computing trust chain isolation

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