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Testable critical path selection considering process variation

Testable critical path selection considering process variati...

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作者： Fu, Xiang Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academic of Science Beijing 100190 China Graduate University of Chinese Academic of Sciences Beijing 100039 China

Critical path selection is very important in delay testing. Critical paths found by conventional static timing analysis (STA) tools are inadequate to represent the real timing of the circuit, since neither the testability of paths nor the statistical variation of cell delays caused by process variation is considered. This paper proposed a novel path selection method considering process variation. The circuit is firstly simplified by eliminating non-critical edges under statistical timing model, and then divided into sub-circuits, while each sub-circuit has only one prime input (PI) and one prime output (PO). Critical paths are selected only in critical sub-circuits. The concept of partially critical edges (PCEs) and completely critical edges (CCEs) are introduced to speed up the path selection procedure. Two path selection strategies are also presented to search for a testable critical path set to cover all the critical edges. The experimental results showed that the proposed circuit division approach is efficient in path number reduction, and PCEs and CCEs play an important role as a guideline during path selection. Copyright © 2010 The institute of Electronics.

关键词： Delay circuits

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VMGuard: An integrity monitoring system for management virtual machines

VMGuard: An integrity monitoring system for management virtu...

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16th IEEE International Conference on Parallel and Distributed Systems, ICPADS 2010

作者： Fang, Haifeng Zhao, Yiqiang Zang, Hongyong Huang, H. Howie Song, Ying Sun, Yuzhong Liu, Zhiyong Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China George Washington University WA United States

ISBN: (纸本)9780769543079

A cloud computing provider can dynamically allocate virtual machines (VM) based on the needs of the customers, while maintaining the privileged access to the Management Virtual Machine that directly manages the hardware and supports the guest VMs. The customers must trust the cloud providers to protect the confidentiality and integrity of their applications and data. However, as the VMs from different customers are running on the same host, an attack to the management virtual machine will easily lead to the compromise of the guest VMs. Therefore, it is critical for a cloud computing system to ensure the trustworthiness of management VMs. To this end, we propose VMGuard, an integrity monitoring and detecting system for management virtual machines in a distributed environment. VMGuard utilizes a special VM, Guard Domain, which runs on each physical node to monitor the co-resident management VMs. The integrity measurements collected by the Guard Domains are sent to the VMGuard server for safe store and independent analysis. The experimental evaluation of a Xen-based prototype shows that VMGuard can quickly detect the root kit attacks while the performance overhead is low. © 2010 IEEE.

关键词： Virtual machine

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Virtualizing modern high-speed interconnection networks with performance and scalability

Virtualizing modern high-speed interconnection networks with...

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作者： Li, Bo Huo, Zhigang Zhang, Panyong Meng, Dan National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769542201

As one of the most important enabling technologies of cloud computing, virtualization brings to HPC good manageability, online system maintenance, performance isolation and fault isolation. Furthermore, previous study on VMM-bypass I/O that virtualizes OS-bypass networks (e.g. Infini- Band) relieved the worry of performance degradation coming along with virtualization. In this paper, we address the scalability challenges imposed upon OS-bypass networks under virtualized environments. The eXtended Reliable Connection (XRC) transport, proposed in modern high-speed interconnection networks to address the scalability problem in large scale applications, would not work in virtualized environments. To solve the problem, we propose VM-proof XRC design to eliminate the scalability gap between virtualized and native environments. Prototype evaluation shows that the virtualization of modern high-speed interconnection networks could get the same raw performance and scalability as in native non-virtualized environment with our VM-proof XRC design. The connection memory scalability shows a potential of 16 times improvement on virtualized clusters composed of 16-core nodes. © 2010 IEEE.

关键词： Scalability

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DCMTs: Supporting dynamically created migratory threads

DCMTs: Supporting dynamically created migratory threads

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International Conference on Computational Science and Engineering

作者： Zhu, Yueting Zhang, Wu Jiang, Hai Lei, Yu Peng, Junjie Department of Computer Science and Engineering Shanghai University Shanghai China Department of Computer Science Arkansas State University Jonesboro AR United States Department of Computer Science and Engineering University of Texas Arlington TX United States Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9780769543239

Thread migration is an effective technique for fault resilience and load balancing in high performance computing. However, flexible thread migration is not easy to achieve. In this paper, we present an approach to creating migratory threads dynamically at application level. The targets must be executable source files. Compared to the static ones, the number of threads created during migration with the new scheme is independent from the context. Various thread cases are considered for migration. Thread state is handled at application level. Variables are saved in structures in C language for speedy state construction. In order to solve the inability of traditional methods in tracking the created threads, a tree of active function calls is used to record the callback. The preprocessor of the proposed one is written in YACC for accuracy and programmability. The migration enabling process is transparent to programmers with the help of the preprocess. The experimental results have demonstrated the effectiveness of this approach. © 2010 IEEE.

关键词： Fault tolerance

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Fast facial fitting based on mixture appearance model with 3D constraint

Fast facial fitting based on mixture appearance model with 3...

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Chinese Conference on Pattern Recognition

作者： Huang, Xiangsheng Gong, Lujin Wang, Xiaoyan Institute of Automation Chinese Academy of Sciences Beijing 100190 China State Key Laboratory of Scientific and Engineering Computing Institute of Computational Mathematics and Scientific/Engineering Computing AMSS Beijing 100190 China College of Computer Science and Technology Zhejiang University of Technology Hangzhou 310023 China

ISBN: (纸本)9781424472109

Fast facial points fitting plays an important role in applications such as Human-computer Interaction, entertainment, surveillance, and is highly relevant to the techniques of facial expression analysis, face recognition, 3D face model generation, etc. Active Appearance Models (AAMs) are generative models commonly used to fit face. They are sensitive to illumination and expression changes because they use only raw intensity to build observation models. In this paper, a real time facial points fitting approach using mixture observation models is presented. Furthermore, the 3D modes are used to constrain the AAM so that it can only generate model instances that can also be generated with the 3D modes. Finally, we give a derivative process for fast energy minimization using the inverse compositional algorithm. A coarse-to-fine fitting strategy is used for realtime and robust facial points fitting. We apply this algorithm to facial expression cloning of 3D Avatar system. Experimental results demonstrate that fitting the AAM with mixture observation models and 3D constraint outperforms other classical algorithms. ©2010 IEEE.

关键词： Mixtures

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DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance

DMA cache: Using on-chip storage to architecturally separate...

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IEEE Symposium on High-Performance computer architecture

作者： Dan Tang Yungang Bao Weiwu Hu Mingyu Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

ISBN: (纸本)9781424456581

As technology advances both in increasing bandwidth and in reducing latency for I/O buses and devices, moving I/O data in/out memory has become critical. In this paper, we have observed the different characteristics of I/O and CPU memory reference behavior, and found the potential benefits of separating I/O data from CPU data. We propose a DMA cache technique to store I/O data in dedicated on-chip storage and present two DMA cache designs. The first design, Decoupled DMA Cache (DDC), adopts additional on-chip storage as the DMA cache to buffer I/O data. The second design, Partition-Based DMA Cache (PBDC), does not require additional on-chip storage, but can dynamically use some ways of the processor's last level cache (LLC) as the DMA cache. We have implemented and evaluated the two DMA cache designs by using an FPGA-based emulation platform and the memory reference traces of real-world applications. Experimental results show that, compared with the existing snooping-cache scheme, DDC can reduce memory access latency (in bus cycles) by 34.8% on average (up to 58.4%), while PBDC can achieve about 80% of DDC's performance improvements despite no additional on-chip storage.

关键词： Cache storage Delay Bandwidth Buffer storage System-on-a-chip Laboratories computer architecture Emulation Throughput Hard disks

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Optimizing network paravirtualization with static shared memory pipe

Optimizing network paravirtualization with static shared mem...

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WASE International Conference on Information Engineering

作者： Zang, Hongyong Gu, Kuiyan Sun, Yuzhong Meng, Dan Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University of Chinese Academy of Sciences Beijing 100049 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Dongxin Geology Research Institute of Shengli Oilfield Sinopec Dongying Shandong 257094 China

ISBN: (纸本)9780769540801

Virtual machine technology can provide high server utilization and service consolidation on an individual physical machine, and gains acceptance in diverse fields. In a growing number of contexts, many situations require high-performance network virtualization. Paravirtualized network system adopts split driver model, and uses dynamic shared memory mechanism for communication between unprivileged guest domain and isolated driver domain. The dynamic shared memory mechanism introduces extra per-packet overheads, such as additional hypercalls and grant table operations. In this paper, we have implemented a new method called STAMP (static shared memory pipe), which uses static shared memory mechanism on Xen platform. STAMP comprises a two-way lockless producer-consumer circular buffer to carry network packets between split drivers. Once STAMP is established between guest domain and isolated driver domain, all packets are transferred through it to avoid extra overheads introduced by dynamic shared memory mechanism. In our evaluations, STAMP achieves availability and high efficiency, especially for scenarios of small messages. These results make the static shared memory mechanism an attractive solution for network paravirtualization. © 2010 IEEE.

关键词： Virtual machine

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On generation of a universal path candidate set containing testable long paths

On generation of a universal path candidate set containing t...

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IEEE International Test Conference

作者： Zijian He Tao Lv Huawei Li Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

We propose an efficient algorithm on generation of a universal path candidate set U that contains testable long paths for delay testing. Some strategies are presented to speed up the depth-first search procedure of U generation, targeting the reduction of checking times of sensitization criteria. Experimental results illustrate that our approach achieves an 8X speedup on average in comparison with the traditional depth-first search approach.

关键词： Automatic test pattern generation

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A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only) 10

A multi-FPGA based platform for emulating a 100m-transistor-...

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Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays

作者： Huandong Wang Xiang Gao Yunji Chen Dan Tang Weiwu Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781605589114

This paper describes a multi-FPGA based platform for emulating the Loongson-2G micro-processor on different mother boards. This platform is developed targeting at verification and evaluation of the Loongson-2G micro-processor, which is the next generation of Loongson-2 family, composed by one four-issue, out-of-order execution way 64-bit MIPS-compatible processor core named GS464, one 1M byte secondary Cache, one HyperTransport IO interface, one DDR2/3 memory interface and some other low speed IO interfaces. Most parts of this micro-process are mapped into the multi-FPGA based platform which consists two Vertex-5 330 FPGA chips. Semi-custom partitioning tactics within the entire design flow are developed to synthesize the whole designed into the multi-FPGA based platform. Modifications in architectural level are applied to the original architecture of the chip, in order to make it easy to be partitioned into two parts. High speed SEDES of HyperTransport IO link and DDR2/3 memory interface are emulated by using several clocks with different clock phases. To resolve the problem that hard to debug in FPGA system, a method by software probe with help of injected hardware modules in FPGA is developed and used to debug the problem causing by behavior mismatching between the ASIC ram block and the FPGA ram block. Some evaluation work on performance of Loongson-2G is done on this multi-FPGA based platform as pre-silicon test. To the authors' knowledge, there has been no previous work on such a big design used for verification and evaluation.

关键词： multi-fpga emulation loongson verification evaluation fpga

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Using Index in the MapReduce Framework

Using Index in the MapReduce Framework

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International Asia-Pacific Web Conference (APWEB)

作者： Mingyuan An Yang Wang Weiping Wang Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China Institute of Computing Technology Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

MapReduce is a programming framework introduced by Google for large-scale data processing. It is usually used in a scan-centric fashion where all the data are split into blocks and Maps are generated for each block to scan and process the data in the block, then Reduces merge outputs from all the Maps. When a query intends to process only a subset of the data selected by a predicate, this brute-force method may cause extra I/O overhead spent on irrelevant data, and the overhead for initiating so many Maps may be non-trivial given that the actually interesting data for the query is comparatively small in volume. We propose an approach to integrate the index into the MapReduce execution in which only an appropriate number of Maps are generated, each of which accesses the data using an index. This approach incurs random I/O and remote access to data, so the overall performance depends on both system parameters and the query characteristics. We build a cost model for both this index access execution and the traditional full scan execution. This cost model can be used to choose between the two execution modes before executing a query. Experiments show that the index access execution can greatly outperform full scan execution when the selectivity of the predicate is low, and the cost model predicts the actual execution cost very well so can be used to determine the execution plan for a query.

关键词： Flash memory Indexing computer science Delay Tree data structures Energy efficiency Nonvolatile memory Costs Mechanical factors Energy storage

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