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2010 2nd International Conference on Software technology and Engineering, ICSTE 2010

作者： Li, Qing'an He, Yanxiang Chen, Yong Wu, Wei Xu, Wenwen School of Computer Wuhan University Wuhan 430072 China State Key Laboratory of Software Engineering Wuhan University Wuhan 430072 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

ISBN: (纸本)9781424486656

Page switching is a technique that increases the memory in microcontrollers without extending the address buses. This technique is widely used in the design of 8-bit MCUs. In this paper, we present an algorithm to reduce the overhead of page switching. To pursue small code size, we place the emphasis on the allocation of functions into suitable pages with a heuristic algorithm, thereby the cost-effective placement of page selection instructions. Our experimental results showed the optimization achieved a reduction in code size of 13.2 percent. © 2010 IEEE.

关键词： Cost effectiveness

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Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors 10

Performance-asymmetry-aware topology virtualization for defe...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Lei Zhang Yue Yu Jianbo Dong Yinhe Han Shangping Ren Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Department of Computer Science Illinois Institute of Technology USA

ISBN: (纸本)9783981080162

Topology virtualization techniques are proposed for NoC-based many-core processors with core-level redundancy to isolate hardware changes caused by on-chip defective cores. Prior work focuses on homogeneous cores with symmetric performance and optimizes on-chip communication only. However, core-to-core performance asymmetry due to manufacturing process variations poses new challenges for constructing virtual topologies. Lower performance cores may scatter over a virtual topology, while operating systems typically allocate tasks to continuous cores. As a result, parallel applications are probably assigned to a region containing many slower cores that become bottlenecks. To tackle the above problem, in this paper we present a novel performance-asymmetry-aware reconfiguration algorithm Bubble-Up based on a new metric called core fragmentation factor (CFF). Bubble-Up can arrange cores with similar performance closer, yet maintaining reasonable hop distances between virtual neighbors, thus accelerating applications with higher degree of parallelism, without changing existing allocation strategies for OS. Experimental results show its effectiveness.

关键词： Network topology Network-on-a-chip Programming profession Hardware System-on-a-chip Manufacturing processes Scattering Operating systems Parallel processing Throughput

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Outlier Detection for Learning-Based Optimizing Compiler

Outlier Detection for Learning-Based Optimizing Compiler

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Japan-China Joint Workshop on Frontier of computer Science and technology (FCST)

作者： Shun Long Weiheng Zhu Department of Computer Science Jinan University Guangzhou China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

Modern compilers use machine learning to find from their prior experience useful heuristics for new programs encountered in order to accelerate the optimization process. However, prior experience might not be applicable for outlier programs with unfamiliar code features. This paper presents a Reverse K-nearest neighbor (RKNN) algorithm based approach for outlier detection. The compiler can therefore launch a search within an optimization space when outlier programs are encountered, or directly apply its experience to non-outliers. Preliminary experimental results demonstrate the effectiveness of the approach.

关键词： Optimization Program processors Training Kernel Benchmark testing Arrays Nearest neighbor searches

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On synchronization and evaluation method of chipped many-core processor

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Jisuanji Xuebao/Chinese Journal of computers 2010年第10期33卷 1777-1787页

作者： Xu, Wei-Zhi Song, Feng-Long Liu, Zhi-Yong Fan, Dong-Rui Yu, Lei Zhang, Shuai Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acad. of Sci. Beijing 100190 China Graduate University of Chinese Acad. of Sci. Beijing 100039 China

Synchronization schemes are critical for on-chip multi-core and many-core processor to execute correctly and communicate cooperatively. The efficiency of the synchronization is very important for the processor. In this paper, for on-chip many-core architecture, three types of synchronization schemes are proposed. That is, two types of coarse-grain synchronization schemes based on dedicated hardware support and atomic operation, and a fine-grain synchronization scheme based on Full/Empty bit. Then, the evaluation criterions and methods are proposed, in which quantitative evaluation micro-benchmarks are designed for coarse-grain synchronization schemes. Finally, the coarse-grain synchronization schemes are evaluated via a many-core architecture simulator, i.e., Godson-T, and AMD Opteron commercial on-chip multi-processor using pThread multi-thread program model. The results show that hardware support improves the performance of the synchronization obviously for on-chip many-core processor, and the performance loss of the traditional synchronization scheme based on atomic instructions is caused by the waiting cost of load imbalance and serialization on synchronization point mostly.

关键词： Synchronization

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Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs 10

Accelerating Lightpath setup via broadcasting in binary-tree...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Binzhang Fu Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9783981080162

In this paper, we propose a binary-tree waveguide connected Optical-Network-on-Chip (ONoC) to accelerate the establishment of the lightpath. By broadcasting the control data in the proposed power-efficient binary-tree waveguide, the maximal hops for establishing lightpath is reduced to two. With extensive simulations and analysis, we demonstrate that the proposed ONoC significantly reduces the setup time, and then the packet latency.

关键词： Optical waveguides Acceleration Broadcasting Network-on-a-chip Optical interconnections Delay Optical modulation Logic Microcavities Optical devices

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An abstraction-guided simulation approach using Markov models for microprocessor verification 10

An abstraction-guided simulation approach using Markov model...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Tao Zhang Tao Lv Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9783981080162

In order to combine the power of simulation-based and formal techniques, semi-formal methods have been widely explored. Among these methods, abstraction-guided simulation is a quite promising one. In this paper, we propose an abstraction-guided simulation approach aiming to cover hard-to-reach states in functional verification of microprocessors. A Markov model is constructed utilizing the high level functional specification, i.e. ISA. Such model integrates vector correlations. Furthermore, several strategies utilizing abstraction information are proposed as an effective guidance to the test generation. Experimental results on two complex microprocessors show that our approach is more efficient in covering hard-to-reach states than similar methods. Comparing with some work with other intelligent engines, our approach could guarantee higher hit ratio of target states without efficiency loss.

关键词： Microprocessors Testing Computational modeling Engines Data mining computer simulation Power system modeling Laboratories computer architecture Instruction sets

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A general method to make multi-clock system deterministic 10

A general method to make multi-clock system deterministic

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Design, Automation and Test in Europe Conference and Exhibition

作者： Menghao Su Yunji Chen Xiang Gao Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9783981080162

Nondeterminism of multi-clock systems often complicates various system validation processes such as post silicon debugging and at-speed testing, which has brought many difficulties to system designers and testers. The major source of nondeterministic behaviors is clock domain crossing, because the clocks that determine the timing of events are sensitive to variations. In this paper, we propose a general method to eliminate the nondeterminism resulted from clock domain crossing. This method does not assume any specific relationship among the clocks. Instead, to adapt to various clock conditions, an automatic configuration procedure and a periodic error canceling mechanism, which only require trivial hardware support, are proposed by analyzing the deterministic boundaries theoretically. To demonstrate the applicability of our method in practice, we implement it on a FPGA platform. Experiment results validate that the performance loss brought by our method over conventional multi-clock FIFO is less than 2%.

关键词： Clocks Circuit testing Frequency synchronization Frequency estimation Debugging Hardware Field programmable gate arrays Silicon System testing Performance loss

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An on-chip clock generation scheme for faster-than-at-speed delay testing 10

An on-chip clock generation scheme for faster-than-at-speed ...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9783981080162

Faster-than-at-speed testing provides an effective way for detecting and debugging small delay defects in modern fabricated chips. However, the use of external automatic test equipment for faster-than-at-speed delay testing could be costly. In this paper, we present an on-chip clock generation scheme which facilitates faster-than-at-speed delay testing for both launch on capture and launch on shift test frameworks. The required test clock frequency with a high resolution can be obtained by specifying the information in the test patterns, which is then shifted into the delay control stages to configure the launch and capture clock generation circuit (LCCG) embedded on-chip. Similarly, the control information for selecting various test frameworks and clock signals can also be embedded in the test patterns. Experimental results are presented to validate the proposed scheme.

关键词： Clocks Delay Circuit testing Lab-on-a-chip Frequency Automatic testing Timing System testing Phase locked loops Circuit faults

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Diagnosis of multiple arbitrary faults with mask and reinforcement effect 10

Diagnosis of multiple arbitrary faults with mask and reinfor...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Jing Ye Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9783981080162

We propose a multiple-fault diagnosis method with high diagnosability, resolution, first-hit and short run time. The method has no assumption on fault models, thus can diagnose arbitrary faults. To cope with the multiple-fault mask and reinforcement effect, two key techniques of construction and scoring of fault-tuple equivalence trees are introduced to choose and rank the final candidate locations. Experimental results show that, when the circuits have 2 arbitrary faults, the average diagnosability and resolution are 98% and 0.95, respectively, with the best case 100% and 1.00. Moreover, in average, even when 21 arbitrary faults exist, our method can still identify 93% of them with the resolution 0.78, increased by 41% and 39% in comparison with the latest work where the diagnosability and resolution are 66% and 0.56. Finally, 96% of our top-ranked candidate locations are actual fault locations.

关键词： Fault diagnosis Circuit faults Testing Fault location Integrated circuit yield Time to market Costs Automatic test pattern generation Test pattern generators Laboratories

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Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors

Address Remapping for Static NUCA in NoC-Based Degradable Ch...

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Pacific Rim International Symposium on Dependable computing

作者： Ying Wang Lei Zhang Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Large scale Chip-Multiprocessors (CMPs) generally employ Network-on-Chip (NoC) to connect the last level cache (LLC), which is generally organized as distributed NUCA (non-uniform cache access) arrays for scalability and efficiency. On the other hand, aggressive technology scaling induces severe reliability problems, causing on-chip components (e.g., cores, cache banks, routers) failure due to manufacture defects or on-line hardware faults. Typical degradable CMPs should possess the ability to work around defects by disabling faulty components. For static NUCA architecture, when cache banks attached to a computing node are disabled, however, certain physical address sections will no longer be accessible. Prior approaches such as sets reduction introduced in Intel Xeon processor 7100 series enable turning off cache banks by masking certain sets bits in physical address1, which greatly wastes cache capacity. In this paper, we propose to tackle the above problem in a finer granularity to restrict the capacity loss in NUCA cache. Cache accesses to isolated nodes are redirected based on the utility-driven address remapping scheme that reduces data blocks conflicts in fault-tolerant shared-LLC. We evaluate our technique using GEMS simulator. Experimental results show that address remapping achieves significant improvement over the conventional cache sizing scheme.

关键词： Tiles Nickel Hardware Fault tolerance Fault tolerant systems Prediction algorithms computer architecture

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