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Asian Test Symposium (ATS)

作者： Jing Ye Xiaolin Zhang Yu Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

Volume diagnosis plays an important role in the yield learning process. To get a high quality diagnosis result, patterns with high distinguish ability are essential. However, the test patterns used by volume diagnosis commonly have low distinguish ability to specific faults. In our experiments, we observe that on average, under automatic generated test patterns, faults in the same fan out free region (FFR) account for only 6% of all possible fault pairs, but their share in total indistinguishable faults is 70%, faults in different FFRs but with the same observation points account for 4% of all fault pairs, but their share in total indistinguishable faults is 22%. Exploiting this fact that faults in the same FFRs are harder to be distinguished, we propose an Automatic Diagnostic Pattern Generation (ADPG) method named Substantial Fault Pairs at-A-Time (SFPAT)-ADPG. By applying a transformed circuit and a new fault list to an existing Automatic Test Pattern Generation (ATPG) tool, we generate the compressed test patterns which are also the diagnostic patterns with high distinguish ability for the original circuit. Experiments on ISCAS'89 and ITC'99 benchmark circuits show the effectiveness of the proposed SFPAT-ADPG method.

关键词： Circuit faults Automatic test pattern generation Benchmark testing Logic gates Transforms Integrated circuit modeling

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Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power

Design of Low-Cost High-Performance Floating-Point Fused Mul...

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International Conference on VLSI Design

作者： Zichu Qi Qi Guo Ge Zhang Xiangku Li Weiwu Hu Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

ISBN: (纸本)9781424455416

This paper presents a floating-point fused multiply-add (FMA) unit with low-cost and low power techniques. To improve the performance, two single-precision operations can be performed concurrently with one double-precision datapath, which is very useful in multimedia and even scientific applications. Moreover, to reduce the additional area costs for supporting two single-precision operations in parallel, multiple double-precision units, i.e., the multiplier, shifter and adder, are reused as much as possible. A modified dual-path algorithm is proposed by classifying the exponent difference into three cases and implementing them with close and far paths, which can reduce latency and facilitate lowering power consumption by enabling only one of the two paths. In addition, in case of FADD instructions, the multiplier in the first stage is bypassed and kept in stable mode, which can significantly improve FADD instruction performance and lower power consumption. The overall FMA unit has a latency of 4 cycles while the FADD operation has 3 cycles. Each cycle has a time delay of about 0.66 ns in the ST 65 nm CMOS technology. Compared with the conventional double-precision FMA, about 13% delay is reduced and about 22% area is increased, which is acceptable since two single-precision results can be generated simultaneously.

关键词： Costs Energy consumption CMOS technology Hardware Throughput Very large scale integration Laboratories computer architecture Delay effects Roundoff errors

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Godson-T:An Efficient Many-Core architecture for Parallel Program Executions

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Journal of computer Science & technology 2009年第6期24卷 1061-1073页

作者：范东睿袁楠张军超周永彬林伟宋风龙叶笑春黄河余磊龙国平张浩刘磊 Key Laboratory of Computer Systems and Architecture Institute of Computing Technology Chinese Academy of Sciences

Moore＇s law will grant computer architects ever more transistors for the foreseeable future, and the challenge is how to use them to deliver efficient performance and flexible programmability. We propose a many-core architecture, Godson- T, to attack this challenge. On the one hand, Godson-T features a region-based cache coherence protocol, asynchronous data transfer agents and hardware-supported synchronization mechanisms, to provide full potential for the high efficiency of the on-chip resource utilization. On the other hand, Godson-T features a highly efficient runtime system, a Pthreadslike programming model, and versatile parallel libraries, which make this many-core design flexibly programmable. This hardware/software cooperating design methodology bridges the high-end computing with mass programmers. Experimental evaluations are conducted on a cycle-accurate simulator of Godson-T. The results show that the proposed architecture has good scalability, fast synchronization, high computational efficiency, and flexible programmability.

关键词： many-core parallel computing multithread data communication thread synchronization runtime system

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P2CLRAF: An Pre-and Post-silicon Cooperated Circuit Lifetime Reliability Analysis Framework

P2CLRAF: An Pre-and Post-silicon Cooperated Circuit Lifetime...

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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Song Jin Yinhe Han Huawei Li Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing P.R. China Graduate University of Chinese Academy of Sciences Beijing P.R. China

Statistical static timing analysis (SSTA) considering process variation and aging effects is usually used to analyze circuit lifetime reliability at design phase. A key challenge for statistical lifetime reliability analysis is that an accurate statistical timing model is needed to carefully model practical variation distribution as well as delay correlation. In this work, P2CLRAF, a circuit lifetime reliability analysis framework is proposed. It calibrates presilicon SSTA result by learning the collected data from path delay testing at post-silicon timing validation phase. A neural network inside P2CLRAF is trained to learn variation distribution and delay correlation based on the statistic of path delay testing. The learned information is then fed back to SSTA to further improve the accuracy of circuit lifetime reliability analysis. Experimental results demonstrate the effectiveness of the proposed analysis framework.

关键词： Lifetime Reliability Process Variation NBTI

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Fast Facial Fitting Based on Mixture Appearance Model with 3D Constraint

Fast Facial Fitting Based on Mixture Appearance Model with 3...

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Chinese Conference on Pattern Recognition (CCPR)

作者： Xiangsheng Huang Lujin Gong Xiaoyan Wang Institute of Automation Chinese Academy and Sciences Beijing China State Key Laboratory of Scientific and Engineering Computing AMSS Institute of Computational Mathematics and Scientific/Engineering Computing Chinese Academy and Sciences Beijing China College of Computer Science and Technology Zhejiang University of Technology Hangzhou China

Fast facial points fitting plays an important role in applications such as Human-computer Interaction, entertainment, surveillance, and is highly relevant to the techniques of facial expression analysis, face recognition, 3D face model generation, etc. Active Appearance Models (AAMs) are generative models commonly used to fit face. They are sensitive to illumination and expression changes because they use only raw intensity to build observation models. In this paper, a real time facial points fitting approach using mixture observation models is presented. Furthermore, the 3D modes are used to constrain the AAM so that it can only generate model instances that can also be generated with the 3D modes. Finally, we give a derivative process for fast energy minimization using the inverse compositional algorithm. A coarse-to-fine fitting strategy is used for realtime and robust facial points fitting. We apply this algorithm to facial expression cloning of 3D Avatar system. Experimental results demonstrate that fitting the AAM with mixture observation models and 3D constraint outperforms other classical algorithms.

关键词： Three dimensional displays Shape Active appearance model Solid modeling Face Pixel Robustness

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SimK:A Large-Scale Parallel Simulation Engine

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Journal of computer Science & technology 2009年第6期24卷 1048-1060页

作者：许建卫陈明宇郑规曹政吕慧伟孙凝晖 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Simulation is an important method to evaluate future computer systems. Currently microprocessor architecture has switched to parallel, but almost all simulators remained at sequential stage, and the advantages brought by multi-core or many-core processors cannot be utilized. This paper presents a parallel simulator engine （SimK） towards the prevalent SMP/CMP platform, aiming at large-scale fine-grained computer system simulation. In this paper, highly efficient synchronization, communication and buffer management policies used in SimK are introduced, and a novel lock-free scheduling mechanism that avoids using any atomic instructions is presented. To deal with the load fluctuation at light load case, a cooperated dynamic task migration scheme is proposed. Based on SimK, we have developed large-scale parallel simulators HppSim and HppNetSim, which simulate a full supercomputer system and its interconnection network respectively. Results show that HppSim and HppNetSim both gain sound speedup with multiple processors, and the best normalized speedup reaches 14.95X on a two-way quad-core server.

关键词： large scale system simulation fine-grained synchronization simulation framework lock-free synchronization

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VMGuard: An Integrity Monitoring System for Management Virtual Machines

VMGuard: An Integrity Monitoring System for Management Virtu...

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International Conference on Parallel and Distributed Systems (ICPADS)

作者： Haifeng Fang Yiqiang Zhao Hongyong Zang H. Howie Huang Ying Song Yuzhong Sun Zhiyong Liu University of the Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China George Washington University Washington D.C. DC USA

A cloud computing provider can dynamically allocate virtual machines (VM) based on the needs of the customers, while maintaining the privileged access to the Management Virtual Machine that directly manages the hardware and supports the guest VMs. The customers must trust the cloud providers to protect the confidentiality and integrity of their applications and data. However, as the VMs from different customers are running on the same host, an attack to the management virtual machine will easily lead to the compromise of the guest VMs. Therefore, it is critical for a cloud computing system to ensure the trustworthiness of management VMs. To this end, we propose VMGuard, an integrity monitoring and detecting system for management virtual machines in a distributed environment. VMGuard utilizes a special VM, Guard Domain, which runs on each physical node to monitor the co-resident management VMs. The integrity measurements collected by the Guard Domains are sent to the VMGuard server for safe store and independent analysis. The experimental evaluation of a Xen-based prototype shows that VMGuard can quickly detect the root kit attacks while the performance overhead is low.

关键词： Driver circuits Kernel Servers Monitoring Engines Virtual machining Area measurement

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Quantum state Reduction for Universal Measurement Based Computation

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Physical Review Letters 2010年第2期105卷 020502-020502页

作者： Xie Chen Runyao Duan Zhengfeng Ji Bei Zeng Department of Physics Massachusetts Institute of Technology Cambridge Massachusetts USA Centre for Quantum Computation and Intelligent Systems (QCIS) Faculty of Engineering and Information Technology University of Technology Sydney NSW Australia Department of Computer Science and Technology Tsinghua National Laboratory for Information Science and Technology Tsinghua University Beijing China Perimeter Institute for Theoretical Physics Waterloo Ontario Canada State Key Laboratory of Computer Science Institute of Software Chinese Academy of Sciences Beijing China Institute for Quantum Computing University of Waterloo Waterloo Ontario Canada Department of Combinatorics and Optimization University of Waterloo Waterloo Ontario Canada

Measurement based quantum computation, which requires only single particle measurements on a universal resource state to achieve the full power of quantum computing, has been recognized as one of the most promising models for the physical realization of quantum computers. Despite considerable progress in the past decade, it remains a great challenge to search for new universal resource states with naturally occurring Hamiltonians and to better understand the entanglement structure of these kinds of states. Here we show that most of the resource states currently known can be reduced to the cluster state, the first known universal resource state, via adaptive local measurements at a constant cost. This new quantum state reduction scheme provides simpler proofs of universality of resource states and opens up plenty of space to the search of new resource states.

关键词： Quantum computers

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Selected Crosstalk Avoidance Code for Reliable Network-on-Chip

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Journal of computer Science & technology 2009年第6期24卷 1074-1085页

作者：张颖李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Graduate School of the Chinese Academy of Sciences

With the shrink of the technology into nanometer scale, network-on-chip （NOC） has become a reasonable solution for connecting plenty of IP blocks on a single chip. But it suffers from both crosstalk effects and single event upset （SEU）, especially crosstalk-induced delay, which may constrain the overall performance of NOC. In this paper, we introduce a reliable NOC design using a code with the capability of both crosstalk avoidance and single error correction. Such a code, named selected crosstalk avoidance code （SCAC） in our previous work, joins crosstalk avoidance code （CAC） and error correction code （ECC） together through codeword selection from an original CAC codeword set. It can handle possible error caused by either crosstalk effects or SEU. When designing a reliable NOC, data are encoded to SCAC codewords and can be transmitted rapidly and reliably across NOC. Experimental results show that the NOC design with SCAC achieves higher performance and is reliable to tolerate single errors. Compared with previous crosstalk avoidance methods, SCAC reduces wire overhead, power dissipation and the total delay. When SCAC is used in NOC, it can save 20% area overhead and reduce 49% power dissipation.

关键词： crosstalk avoidance codeword selection reliable network-on-chip single event upset

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Multi-error-correcting amplitude damping codes

Multi-error-correcting amplitude damping codes

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IEEE International Symposium on Information Theory

作者： Runyao Duan Markus Grassl Zhengfeng Ji Bei Zeng State Key Laboratory of Intelligent Technology and Systems Tsinghua National Laboratory for Information Science and Technology Department of Computer Science and Technology Tsinghua University Beijing China Centre for Quantum Computation and Intelligent Systems (QCIS) Faculty of Engineering and Information Technology University of Technology Sydney NSW Australia Centre for Quantum Technologies National University of Singapore Singapore Perimeter Institute of Theoretical Physics Waterloo ONT Canada State Key Laboratory of Computer Science Institute of Software Chinese Academy and Sciences Beijing China Institute for Quantum Computing and the Department of Combinatorics and Optimization University of Waterloo Waterloo ONT Canada

ISBN: (纸本)9781424478903

We construct new families of multi-error-correcting quantum codes for the amplitude damping channel. Our key observation is that, with proper encoding, two uses of the amplitude damping channel simulate a quantum erasure channel. This allows us to use concatenated codes with quantum erasure-correcting codes as outer codes for correcting multiple amplitude damping errors. Our new codes are degenerate stabilizer codes and have parameters which are better than the amplitude damping codes obtained by any previously known construction.

关键词： Damping Quantum mechanics Quantum computing Error correction codes Noise level Laboratories Phase noise Physics computing Intelligent systems computer science

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