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Automatic architecture design for distributed quantum computing

Chinese Physics B 2024年第12期33卷 45-59页

作者： Ting-Yu Luo Yu-Zhen Zheng Xiang Fu Yu-Xin Deng Shanghai Key Laboratory of Trustworthy Computing East China Normal UniversityShanghai 200062China Institute for Quantum Information&State Key Laboratory of High Performance Computing College of ComputerNational University of Defense TechnologyChangsha 410073China Tianjin Institute of Advanced Technology Tianjin 300459China

In distributed quantum computing(DQC),quantum hardware design mainly focuses on providing as many as possible high-quality inter-chip ***,quantum software tries its best to reduce the required number of remote quantum gates between ***,this“hardware first,software follows”methodology may not fully exploit the potential of *** by classical software-hardware co-design,this paper explores the design space of application-specific DQC *** specifically,we propose Auto Arch,an automated quantum chip network(QCN)structure design *** qubits grouping followed by a customized QCN design,AutoArch can generate a near-optimal DQC architecture suitable for target quantum *** results show that the DQC architecture generated by Auto Arch can outperform other general QCN architectures when executing target quantum algorithms.

关键词： distributed quantum computing quantum architecture quantum circuit partitioning

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Solving the subset sum problem by the quantum Ising model with variational quantum optimization based on conditional values at risk

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Science China(Physics,Mechanics & Astronomy) 2024年第8期67卷 43-55页

作者： Qilin Zheng Miaomiao Yu Pingyu Zhu Yan Wang Weihong Luo Ping Xu Institute for Quantum Information and State Key Laboratory of High Performance Computing College of Computer Science and TechnologyNational University of Defense TechnologyChangsha 410073China Hefei National Laboratory Hefei 230088China

The subset sum problem is a combinatorial optimization problem,and its complexity belongs to the nondeterministic polynomial time complete(NP-Complete)*** problem is widely used in encryption,planning or scheduling,and integer *** accurate search algorithm with polynomial time complexity has not been found,which makes it challenging to be solved on classical *** effectively solve this problem,we translate it into the quantum Ising model and solve it with a variational quantum optimization method based on conditional values at *** proposed model needs only n qubits to encode 2ndimensional search space,which can effectively save the encoding quantum *** model inherits the advantages of variational quantum algorithms and can obtain good performance at shallow circuit depths while being robust to noise,and it is convenient to be deployed in the Noisy Intermediate Scale Quantum *** investigate the effects of the scalability,the variational ansatz type,the variational depth,and noise on the ***,we also discuss the performance of the model under different conditional values at *** computer simulation,the scale can reach more than nine *** selecting the noise type,we construct simulators with different QVs and study the performance of the model with *** addition,we deploy the model on a superconducting quantum computer of the Origin Quantum technology Company and successfully solve the subset sum *** model provides a new perspective for solving the subset sum problem.

关键词： subset sum problem quantum Ising model conditional values at risk variational quantum optimization

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NfvInsight:A Framework for Automatically Deploying and Benchmarking VNF Chains

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Journal of computer Science & technology 2022年第3期37卷 680-698页

作者： Tian-Ni Xu Hai-Feng Sun Di Zhang Xiao-Ming Zhou Xiu-Feng Sui Sa Wang Qun Huang Yun-Gang Bao State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China University of Chinese Academy of Sciences Beijing 100049China School of Information and Electronics Beijing Institute of TechnologyBeijing 100081China Peng Cheng Laboratory Shenzhen 518055China Department of Computer Science and Technology Peking UniversityBeijing 100871China

With the advent of virtualization techniques and software-defined networking(SDN),network function virtualization(NFV)shifts network functions(NFs)from hardware implementations to software appliances,between which exists a performance *** to narrow the gap is an essential issue of current NFV ***,the cumbersomeness of deployment,the water pipe effect of virtual network function(VNF)chains,and the complexity of the system software stack together make it tough to figure out the cause of low performance in the NFV *** pinpoint the NFV system performance,we propose NfvInsight,a framework for automatic deployment and benchmarking VNF *** framework tackles the challenges in NFV performance *** framework components include chain graph generation,automatic deployment,and fine granularity *** design and implementation of each component have their *** the best of our knowledge,we make the first attempt to collect rules forming a knowledge base for generating reasonable chain *** deploys the generated chain graphs automatically,which frees the network operators from executing at least 391 lines of bash commands for a single *** diagnose the performance bottleneck,NfvInsight collects metrics from multiple layers of the software ***,we collect the network stack latency distribution ingeniously,introducing only less than 2.2%*** showcase the convenience and usability of NfvInsight in finding bottlenecks for both VNF chains and the underlying *** our framework,we find several design flaws of the network stack,which are unsuitable for packet forwarding inside one single server under the NFV *** optimization for these flaws gains at most 3x performance improvement.

关键词： network function virtualization(NFV) service chain performance bottleneck network stack latency

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An Efficient Network-on-Chip Router for Dataflow architecture

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Journal of computer Science & technology 2017年第1期32卷 11-25页

作者： Xiao-Wei Shen Xiao-Chun Ye Xu Tan Da Wang Lunkai Zhang Wen-Ming Li Zhi-Min Zhang Dong-Rui Fan Ning-Hui Sun State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing 100049 China Department of Computer Science The University of Chicago IL 60637 U.S.A.

Dataflow architecture has shown its advantages in many high-performance computing cases. In dataflow computing, a large amount of data are frequently transferred among processing elements through the network-on-chip （NoC）. Thus the router design has a significant impact on the performance of dataflow architecture. Common routers are designed for control-flow multi-core architecture and we find they are not suitable for dataflow architecture. In this work, we analyze and extract the features of data transfers in NoCs of dataflow architecture： multiple destinations, high injection rate, and performance sensitive to delay. Based on the three features, we propose a novel and efficient NoC router for dataflow architecture. The proposed router supports multi-destination; thus it can transfer data with multiple destinations in a single transfer. Moreover, the router adopts output buffer to maximize throughput and adopts non-flit packets to minimize transfer delay. Experimental results show that the proposed router can improve the performance of dataflow architecture by 3.6x over a state-of-the-art router.

关键词： multi-destination router network-on-chip dataflow architecture high-performance computing

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Latency critical big data computing in finance

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Journal of Finance and Data Science 2015年第1期1卷 33-41页

作者： Tian, Xinhui Han, Rui Wang, Lei Lu, Gang Zhan, Jianfeng State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China

Analytics based on big data computing can benefit today's banking and financial organizations on many aspects, and provide much valuable information for organizations to achieve more intelligent trading, which can help them to gain a great competitive advantage. However, the large scale of data and the critical latency analytics requirement in finance poses a great challenge for current system architecture. In this paper, we first analyze the challenges brought by the financial latency critical big data computing, then propose a discussion on how to handle these challenges from a perspective of multi-level system. We also talk about current researches on low latency in different system levels. The discussions and conclusions in the paper can be useful to the banking and financial organizations with the critical latency requirement of big data analytics. © 2015 China Science Publishing & Media Ltd.

关键词： Big data Financial analytics Latency

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Fault Tolerance Mechanism in Chip Many-Core Processors

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Tsinghua Science and technology 2007年第S1期12卷 169-174页

作者：张磊韩银和李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences Beijing 100080China

As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N+M is proposed to improve N-core processors’ yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors’ performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8% degradation with negligible computing time.

关键词： chip many-core processors yield fault tolerance reconfiguration network-on-chip

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The propositional normal default logic and the finite/infinite injury priority method

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Science China(Information Sciences) 2017年第9期60卷 99-108页

作者： Wei LI Yuefei SUI Yuhui WANG State Key Laboratory of Software Development Environment Beihang University Key Laboratory of Intelligent Information Processing Institute of Computing TechnologyChinese Academy of Sciences School of Computer and Control Engineering University of Chinese Academy of Sciences

In propositional normal default logic, given a default theory(?, D) and a well-defined ordering of D, there is a method to construct an extension of(?, D) without any injury. To construct a strong extension of(?, D) given a well-defined ordering of D, there may be finite injuries for a default δ∈ D. With approximation deduction ?s in propositional logic, we will show that to construct an extension of(?, D) under a given welldefined ordering of D, there may be infinite injuries for some default δ∈ D.

关键词： default extension strong extension finite/infinite injury priority method recursively enumerable sets

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A reconfigurable index FLASH memory tailored to seed-based genomic sequence comparison algorithms

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Journal of VLSI Signal Processing Systems for Signal, Image, and Video technology 2007年第3期48卷 255-269页

作者： Lavenier, D. Georges, G. Liu, X. IRISA/CNRS Campus de Beaulieu Rennes 35042 France Key Laboratory of Computer System and Architecture Institute of Computing Technology CAS Beijing China

Genomic sequence comparison algorithms represent the basic toolbox for processing large volume of DNA or protein sequences. They are involved both in the systematic scan of databases, mostly for detecting similarities with an unknown sequence, and in preliminary processing before advanced bioinformatics analysis. Due to the exponential growth of genomic data, new solutions are required to keep the computation time reasonable. This paper presents a specific hardware architecture to speed-up seed-based algorithms which are currently the most popular heuristics for detecting alignments. The architecture regroups FLASH and FPGA technologies on a common support, allowing a large amount of data to be rapidly accessed and quickly processed. Experiments on database search and intensive sequence comparison demonstrate a good cost/performance ratio compared to standard approaches. © 2007 Springer Science + Business Media, LLC.

关键词： Flash memory

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Labeled Network Stack: A High-Concurrency and Low-Tail Latency Cloud Server Framework for Massive IoT Devices

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Journal of computer Science & technology 2020年第1期35卷 179-193页

作者： Wen-Li Zhang Ke Liu Yi-Fan Shen Ya-Zhu Lan Hui Song Ming-Yu Chen Yuan-Fei Chen State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China Peng Cheng Laboratory Shenzhen 518000China Zhongke Zhicheng Electronic Technology Company Limited Jining 272000China

Internet of Things(IoT)applications have massive client connections to cloud servers,and the number of networked IoT devices is remarkably *** services require both low-tail latency and high concurrency in *** study aims to determine whether an order of magnitude improvement is possible in tail latency and concurrency in mainstream systems by proposing a hardware-software codesigned labeled network stack(LNS)for future *** key innovation is a cross-layered payload labeling mechanism that distinguishes different requests by payload across the full network stack,including application,TCP/IP,and Ethernet *** type of design enables prioritized data packet processing and forwarding along the full datapath,such that latency-insensitive requests cannot significantly interfere with high-priority *** build a prototype datacenter server to evaluate the LNS design against a commercial X86 server and the mTCP research,using a cloud-supported IoT application *** results show that the LNS design can provide an order of magnitude improvement in tail latency and concurrency.A single datacenter server node can support over 2 million concurrent long-living connections for IoT devices as a 99-percentile tail latency of 50 ms is *** addition,the hardware-software codesign approach remarkably reduces the labeling and prioritization overhead and constrains the interference of high-priority requests to low-priority requests.

关键词： tail latency high concurrency network stack cloud server Internet of Things(IoT)service

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Improved structural modeling based on conserved domain clusters and structure-anchored alignments

Proceedings of the ACM Symposium on Applied Computing

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Proceedings of the ACM Symposium on Applied computing 2007年 128-132页

作者： Zhang, Fa Xu, Lin Liu, Zhiyong Yuan, Bo Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Graduate School Chinese Academy of Science Institute of Computing Technology Chinese Academy of Science Department of Computer Science and Engineering Shanghai Jiaotong University

ISBN: (纸本)1595934804;9781595934802

In this paper, we presented a method to improve structural modeling based on conserved domain clusters and structure-anchored alignments. We first constructed a template library of structural clusters for all conserved sequence domains. Then, for each cluster, we built the profile using the structure and sequence information. Finally we use the profile and structural alignments as anchors to increase the alignment accuracy between a query and its templates. Our preliminary results show that this method can be used for the partial prediction for a majority of known protein sequences with better qualities. Copyright 2007 ACM.

关键词： Proteins

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