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International Conference on Collaborative computing: Networking, Applications and Worksharing (CollaborateCom)

作者： Yan Zhu Zexing Hu Huaixi Wang Hongxin Hu Gail-Joon Ahn Key Laboratory of Network and Software Security Assurance Ministry of Education Peking University China Institute of Computer Science and Technology Peking University Beijing China School of Mathematical Sciences Peking University Beijing China Laboratory of Security Engineering for Future Computing (SEFCOM) Arizona State University Tempe AZ USA

With the wide use of online social networks (OSNs), the problem of data privacy has attracted much attention. Several approaches have been proposed to address this issue. One of privacy management approaches for OSN leverages a key management technique to enable a user to simply post encrypted contents so that only users who can satisfy the associate security policy can derive the key to access the data. However, the key management policies of existing schemes may grant access to unauthorized users and cannot efficiently determine authorized users. In this paper, we propose a collaborative framework which enforces access control for OSN through an innovative key management focused on communities. This framework introduces a community key management based on a new group-oriented convergence cryptosystem, as well as provides an efficient privacy preservation needed in a private OSN. To prove the feasibility of our approach, we also discuss a proof-of-concept implementation of our framework. Experimental results show that our construction can achieve the identified design goals for OSNs with the acceptable performance.

关键词： Cryptography Servers Kernel Data privacy Social network services Communities Collaboration

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A parallel algorithm for computing betweenness centrality

A parallel algorithm for computing betweenness centrality

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38th International Conference on Parallel Processing, ICPP-2009

作者： Tan, Guangming Tu, Dengbiao Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China

ISBN: (纸本)9780769538020

In this paper we present a multi-grained parallel algorithm for computing betweenness centrality, which is extensively used in large-scale network analysis. Our method is based on a novel algorithmic handling of access conflicts for a CREW PRAM algorithm. We propose a proper data-processor mapping, a novel edge-numbering strategy and a new triple array data structure recording the shortest path for eliminating conflicts to access the shared memory. The algorithm requires O(n + m) space and O(nm/p ) ( or O(nm+n2logn /p )) time for unweighted (or weighted) graphs, and it is a work-optimal CREW PRAM algorithm. On current multi-core platforms, our algorithm outperforms the previous algorithm by 2-3 times. © 2009 IEEE.

关键词： Parallel algorithms

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Software and hardware cooperate for 1-D FFT algorithm optimization on multicore processors

Software and hardware cooperate for 1-D FFT algorithm optimi...

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IEEE 9th International Conference on computer and Information technology, CIT 2009

作者： Zhou, Yongbin Zhang, Junchao Fan, Dongrui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

Multicore architecture is becoming a promise to keep Moore's Law and brings a revolution in both research and industry which results new design space for software and architecture. Fast Fourier Transform (FFT), computing intensive and bandwidth intensive, is one of the most popular and important applications in the world. Compared with the computing resource on multicore architecture, the on-chip memory resource is much more expensive because of the limitation of physical chip size. Efficient implementation of FFT algorithm on multicore with good scalability is a challenge for both software and hardware developers. In this paper, supported by the Godson-T architecture, an optimized implementation of 1-D FFT has been developed with matrix transpose conceal and computation/communication overlapping, which achieve more than 30% performance improvement as well as almost 1/3 L2 cache consumption reduce comparing with the base six-step FFT. The limitation of scalability is also analyzed and the conclusion is that on Godson-T when frequency and simultaneous data access happen, the limited access bandwidth of L2 cache is the bottleneck and result in the longer on-chip network latency. © 2009 IEEE.

关键词： Fast Fourier transforms

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Snooping and ordering ring - An efficient cache coherence protocol for ring connected CMP

Snooping and ordering ring - An efficient cache coherence pr...

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15th International Conference on Parallel and Distributed Systems, ICPADS '09

作者： Cao, Fei Liu, Zhiyong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China

ISBN: (纸本)9780769539003

Ring is a promising on-chip interconnection for CMP. It is more scalable than bus and much simpler than packet-switched networks. The ordering property of ring can be used to optimize cache coherence protocol design. Existing ring protocols, such as the snooping ring protocol and the ring-order protocol need a retry and acknowledgement scheme or use the ordering property of the ring respectively to resolve conflict memory requests. A cache coherence protocol named SOR (Snooping and Ordering Ring) is developed for ring connected CMP in this paper. This protocol is based on the snooping ring protocol. But instead of using the acknowledgement and retry scheme, it uses the ordering property of the ring to resolve conflicts, thus can avoid unnecessary retries to improve performance and power efficiency. The L1 snooping results are sent with the requests instead of being delayed, so that many useless snoops can be avoided. Simulation result shows that the average probe slot transports and snoop operations can be reduced by SOR are 47% and 48.9%. The average and maximum performance improvements by SOR are 3.33% and 6%. © 2009 IEEE.

关键词： Packet switching

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Co-optimization of Dynamic/Static Test PoWer in Scan Test

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电子学报(英文版) 2009年第1期18卷 54-58页

作者： WANG Wei HAN Yinhe LI Xiaowei FANG Fang School of Computer and Information Hefei University of Technology Hefei 230009 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China School of Management Hefei University of Technology Hefei 230009 China

Low-power design has become a challenge of test. We propose an effective low-power scan architecture named PowerSluice to minimize power consumption during scan test, which is based on scan chain modifications. On one hand, a kind of blocking logic is inserted into the scan chain to reduce the dynamic power and two kinds of controlling units are also inserted to decrease the leakage power during the shift cycle. On the other hand, using genetic algorithm, the exact values of control signals are found out to control the process. Experiments results indicate that this architecture can effectually reduce power during scan test with probably minimum area cost.

关键词：低功耗设计扫描测试静态测试动态优化合作控制单元电力消耗动态功耗

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Improved meet-in-the-middle attacks on 7-round AES-192 and 8-round AES-256

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Tongxin Xuebao/Journal on Communications 2010年第9 A期31卷 197-201页

作者： Dong, Xiao-Li Hu, Yu-Pu Chen, Jie Li, Shun-Bo Yang, Yang Key Laboratory of Computer Networks and Information Security of Ministry of Education Xidian University Xi'an 710071 China State Key Laboratory of Information Security Institute of Software Chinese Academy of Sciences Beijing 100049 China School of Science Xi'an University of Architecture and Technology Xi'an 710055 China

A new variant of 5-round distinguisher of meet-in-the-middle attack on AES was constructed by exploiting the properties of the round transform of AES. Based on the variant of distinguisher, meet-in-the-middle attacks on 7-round AES-192 and 8-round AES-256 were presented by using the time-memory tradeoff approach. It is shown that the new results are better than the cryptanalytic results presented at FSE2008 on reduced AES in terms of the time complexity and the memory complexity.

关键词： Cryptography

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Column-based RLE in row-oriented database

Column-based RLE in row-oriented database

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2009 International Conference on Cyber-Enabled Distributed computing and Knowledge Discovery, CyberC '09

作者： An, Mingyuan Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424452187

In database systems, disk I/O performance is usually the bottleneck of the whole query processing. Among many techniques, compression is one of the most important ones to reduce disk accesses so to improve system performance. RLE (Run-Length Encoding) is one light-weight compression algorithm which incurs negligible CPU cost. A lot of work show that, although RLE is one of the most effective compression techniques in column-oriented systems, it is very hard to use due to bad value locality in row-oriented systems where values from multiple attributes are stored in the same page. We propose CRLE (Column-based RLE), one compression algorithm to apply RLE to row-oriented data storage. On row-oriented storage page, CRLE can exploit value locality in individual column and encode values from the same column in run-length format. Experiments show that CRLE can lead to very good compression ratio and performance in spite of row-oriented data storage. © 2009 IEEE.

关键词： Query processing

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Juicer: Scalable extraction for thread meta-information of web forum

Juicer: Scalable extraction for thread meta-information of w...

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Pacific Asia Workshop on Intelligence and Security Informatics, PAISI 2009

作者： Guo, Yan Wang, Yu Ding, Guodong Cao, Donglin Zhang, Gang Lv, Yi Institute of Computing Technology Chinese Academy of Sciences China State Key Laboratory of Computer Science Institute of Software Chinese Academy of Sciences China

ISBN: (纸本)9783642013928

In Web forum, thread meta-information contained in list-ofthread of board page provide fundamental data for the further forum mining. This paper describes a complete system named Juicer which was developed as a subsystem for an industrial application that involves forum mining. The task of Juicer is to extract thread meta-information from board pages of a great many of large scale online Web forums, which implies that scalable extraction is required with high accuracy and speed, and minimal user effort for maintenance. Among so many existed approaches about information extraction, we can not find any approach to fully satisfy the requirements, so we present simple scalable extraction approach behind Juicer to achieve the goal. Juicer is constituted by four modules: Template generation, Specifying labeling setting, Automatic extraction, Label assignment. Both experiments and practice show that Juicer successfully satisfied the requirements.

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A low overhead on-chip path delay measurement circuit

A low overhead on-chip path delay measurement circuit

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18th Asian Test Symposium, ATS 2009

作者： Pei, Songwei Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Academy of Sciences Graduate University of Chinese Beijing 100190 China

ISBN: (纸本)9780769538648

In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed method can achieve a large delay measurement range with a small quantity of delay stages. Experimental results show that a significant reduction in both delay measurement time and area overhead can be obtained compared to the previous Vernier Delay Line based delay measurement schemes. In addition, by conducting delay compensation, the proposed method can achieve both improved delay measurement resolution and measurement accuracy. © 2009 IEEE.

关键词： Timing circuits

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A scalable scan architecture for Godson-3 multicore microprocessor

A scalable scan architecture for Godson-3 multicore micropro...

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18th Asian Test Symposium, ATS 2009

作者： Qi, Zichu Liu, Hui Li, Xiangku Wang, Da Han, Yinhe Li, Huawei Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate University of Chinese Academy of Sciences GUCAS Beijing China

ISBN: (纸本)9780769538648

This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (Scalable Mesh of Crossbar) on-chip network and targets high-end applications. Advanced techniques are adopted to achieve the scalable, low-power and low-cost scan architecture at the challenge of limited I/O resources and large scale of transistors. To achieve a scalable and flexible test access, a highly elaborate TAM (Test Access Mechanism) is implemented with supporting multiple test instructions and test modes. Taking advantage of multiple cores embedding in the processor, scan partitions are employed to reduce test power and test time, and test compression with more than 10X compression ratio are utilized to decrease the scan chain length. To further decrease test time, a Data-Synchronous-Comparator (DSC) is proposed for comparing the scan responses of the identical cores. © 2009 IEEE.

关键词： Comparators (optical)

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