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Utility analysis for Internet-oriented server consolidation in VM-based data centers

Utility analysis for Internet-oriented server consolidation ...

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IEEE International Conference on Cluster computing

作者： Ying Song Yanwei Zhang Yuzhong Sun Weisong Shi Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Wayne State University Detroit USA

Server consolidation based on virtualization technology will simplify system administration, reduce the cost of power and physical infrastructure, and improve utilization in today's Internet-service-oriented enterprise data centers. How much power and how many servers for the underlying physical infrastructure are saved via server consolidation in VM-based data centers is of great interest to administrators and designers of those data centers. Various workload consolidations differ in saving power and physical servers for the infrastructure. The impacts caused by virtualization to those concurrent services are fluctuating considerably which may have a great effect on server consolidation. This paper proposes a utility analytic model for Internet-oriented server consolidation in VM-based data centers, modelling the interaction between server arrival requests with several QoS requirements, and capability flowing amongst concurrent services, based on the queuing theory. According to features of those services' workloads, this model can provide the upper bound of consolidated physical servers needed to guarantee QoS with the same loss probability of requests as in dedicated servers. At the same time, it can also evaluate the server consolidation in terms of power and utility of physical servers. Finally, we verify the model via a case study comprised of one e-book database service and one e-commerce Web service, simulated respectively by TPC-W and SPECweb2005 benchmarks. Our experiments show that the model is simple but accurate enough. The VM-based server consolidation saves up to 50% physical infrastructure, up to 53% power, and improves 1.7 times in CPU resource utilization, without any degradation of concurrent services' performance, running on Rainbow - our virtual computing platform.

关键词： Web server Costs Web and internet services Queueing analysis Upper bound Databases Web services Resource management Degradation Concurrent computing

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Mean Shift Based Collaborative Localization with Dynamically Clustering for Wireless Sensor Networks

Mean Shift Based Collaborative Localization with Dynamically...

引用

WRI International Conference on Communications and Mobile computing, CMC

作者： Quan Zhou Xiaowei Li Yongjun Xu Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China Institute of Computing Technology Laboratory of Sensor Networks Chinese Academy and Sciences Beijing China

Mean shift is a nonparametric method to estimate the density gradient, which iteratively computes the mean of observations and shifts to the centroid until reach a predefined end condition. This paper proposes a mean shift based scheme for localization and tracking in wireless sensor *** shift is a generalized framework, and range-free centroid and range-based W-Centrod are both the special cases of this generalized framework. A dynamically clustering protocol is proposed to support the generalized framework. Analysis and simulation results show that the communication overhead and jitter are reduced to 1/3 of traditional algorithms. The positioning accuracy of proposed algorithm with optimal weight increases 28% and 11% in comparison to Centroid and W-Centroid.

关键词： Wireless sensor networks computer networks Clustering algorithms Laboratories Protocols Equations Mobile communication Mobile computing International collaboration computer architecture

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Smallest Enclosing Circle Based Localization Approach for Wireless Sensor Networks

Smallest Enclosing Circle Based Localization Approach for Wi...

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WRI International Conference on Communications and Mobile computing, CMC

作者： Quan Zhou Xiaowei Li Yongjun Xu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Laboratory of Sensor Networks Institute of Computing Technology Chinese Academy and Sciences Beijing China

A novel range-free localization approach, smallest enclosing Circle based Localization (SECL), has been proposed. This approach uses the center of smallest enclosing circle of neighboring anchor nodes to estimate the position of target. Comparing to centroid, SECL considers the geometrical coverage of anchors rather than the mass center of them. Consequently, SECL is robust to imperfect topology, especially when the topology of anchors is depolyed unevenly. Simulation results show that SECL outperforms Centroid by an average of 10%, and even better when the topology is not uniform.

关键词： Wireless sensor networks Network topology computer networks Laboratories Robustness Computational modeling Equations Hardware Mobile communication Mobile computing

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A self-repairable microprocessor

A self-repairable microprocessor

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ISTC/CSTIC 2009 (CISTC)

作者： Xie, Yuanjiang Fu, Xiang He, Zijian Zhao, Yang Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate School of Chinese Academy of Sciences Beijing 100049 China Department of Computer Science and Engineering University of California Riverside 92521 United States

ISBN: (纸本)9781615676460

With increasing defect density, microprocessors, especially the embedded caches, will encounter more faults. Adding spare resources to replace defective components is a widely accepted method for yield enhancement. In this work, a repair method using content addressable memory combined with spare bits, as well as a novel fault injection method is proposed. With the proposed fault injection technique, various numbers and types of faults can be flexibly injected into the silicon. A wireless sensor network system using our self-repairable microprocessor (SRP) is developed to prove the effectiveness of the proposed technique. ©The Electrochemical Society.

关键词： Wireless sensor networks

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Characterizing Betweenness Centrality Algorithm on Multi-core architectures

Characterizing Betweenness Centrality Algorithm on Multi-cor...

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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Dengbiao Tu Guangming Tan Chinese Academy and Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

This paper presents an in-depth analysis of characterization for an irregular application - computing betweenness centrality (BC) - on multicore architectures. BC algorithm is widely used in large scale graph analysis applications, which play an increasingly important role in high performance computing community. Through a joint study of architecture and application, we find that dynamically non-contiguous memory access, unstructured parallelism and low arithmetic intensity in BC program pose an obstacle to an efficient execution on parallel architectures. The experimental results report a comparison between Intel Clovertown and Sun Niagara1 for running such irregular program. Finally, several implications on multicore architecture and programming are proposed.

关键词： computer architecture Multicore processing computer applications Large-scale systems Performance analysis Algorithm design and analysis High performance computing Parallel processing Arithmetic Parallel architectures

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Impact of Hazards on Pattern Selection for Small Delay Defects

Impact of Hazards on Pattern Selection for Small Delay Defec...

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Pacific Rim International Symposium on Dependable computing

作者： Jie Wang Huawei Li Yinghua Min Xiaowei Li Huaguo Liang School of Computer and Information Hefei University of Technology Hefei China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Hazards ubiquitously exist in combinational circuits, and then should be taken into account for delay testing. This paper analyzes the impact of hazards on small-delay defect (SDD) detection, and presents a new test pattern selection method considering hazards. The concept of arrival time window is introduced and the concept of output deviation is redefined to accurately reflect the pattern capability on SDD detection. A new signal transition probability calculation method is presented to calculate output deviation more practical than that without considering hazards. Patterns from an N-detect test set for transition faults are then selected according to their output deviations. Experimental results show that, for the same pattern count, the patterns selected by the proposed method excite more long paths, and are capable of detecting more small delay defects at the early stage of delay testing compared to the method without considering hazards.

关键词： Hazards Circuit testing Circuit faults Automatic test pattern generation Delay effects Timing Clocks Propagation delay Logic testing Crosstalk

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A Low Overhead On-Chip Path Delay Measurement Circuit

A Low Overhead On-Chip Path Delay Measurement Circuit

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Asian Test Symposium (ATS)

作者： Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed method can achieve a large delay measurement range with a small quantity of delay stages. Experimental results show that a significant reduction in both delay measurement time and area overhead can be obtained compared to the previous Vernier Delay Line based delay measurement schemes. In addition, by conducting delay compensation, the proposed method can achieve both improved delay measurement resolution and measurement accuracy.

关键词： Integrated circuit measurements Delay effects Area measurement Time measurement Delay lines Electrical fault detection Fault detection Debugging Circuit faults Added delay

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Small Delay Fault Simulation for Sequential Circuits

Small Delay Fault Simulation for Sequential Circuits

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Pacific Rim International Symposium on Dependable computing

作者： Li Liu Jishun Kuang Huawei Li School of Computer and Communication Hunan University Changsha China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Small-delay faults may escape detection by transition fault patterns, but traditional transition fault simulator can not detect this phenomenon. A fault simulator detecting test escape of small-delay faults is presented. The sizes of the faults are less than one system clock cycle. For our method, the delay distribution in the CUT is considered, and the fault size is quantized as times of the propagation delay in an inverter. By a waveform simulation based on Boolean process, the simulator is able to show the time interval that the fault affects and determine whether the propagation delay exceeds the system clock cycle. It might give ATPG a little of useful information.

关键词： Circuit faults Circuit simulation Sequential circuits Electrical fault detection Fault detection Propagation delay Clocks Circuit testing Inverters Automatic test pattern generation

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A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes

A New Multiple-Round DOR Routing for 2D Network-on-Chip Mesh...

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Pacific Rim International Symposium on Dependable computing

作者： Binzhang Fu Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

The Network-on-Chip (NoC) meshes are limited by the reliability constraint, which impels us to exploit the fault tolerant routing. Particularly, one of the main design issues is minimizing the loss of non-faulty routers at the presence of faults. To address that problem, we propose a new fault tolerant routing, which has the following two distinct advantages: First, it keeps a network deadlock-free by utilizing restricted intermediate nodes rather than adding virtual channels (VC). This characteristic leads to an area-efficient router. Second, in the proposed routing algorithm, the rounds of DOR are not limited by the number of VC's anymore. As a consequence, the number of sacrificed non-faulty routers is significantly reduced. We demonstrate above advantages through extensive simulations. The experimental results show that under the limitation of VC's, the proposed routing algorithm always sacrifices the minimal number of non-faulty routers compared to previous solutions.

关键词： Routing Network-on-a-chip Virtual colonoscopy Fault tolerance System recovery computer networks Region 4 Shape Laboratories computer architecture

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Efficient Physical Design Methodology for Reducing Test Power Dissipation of Scan-Based Designs

Efficient Physical Design Methodology for Reducing Test Powe...

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International Conference on Networking, architecture, and Storage (NAS)

作者： Jun Xu Xiangku Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing China

Scan-based test methodology is used to resolve the sequential-test problem but suffers from high power dissipation. In this paper, we propose a scheme to prevent transitions of scan chain from reflecting into the circuit line. It not only can save 23% power consumption without performance loss, but also can be easily implemented with popular industrial design tools.

关键词： Design methodology Power dissipation Circuit testing Automatic test pattern generation Sequential analysis Registers computer architecture System testing Logic Controllability

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