检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

993 篇 期刊文献
797 篇 会议
1 册 图书

馆藏范围

1,791 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,148 篇 工学
- 721 篇 计算机科学与技术...
- 492 篇 软件工程
- 193 篇 电子科学与技术（可...
- 166 篇 信息与通信工程
- 105 篇 控制科学与工程
- 95 篇 电气工程
- 89 篇 核科学与技术
- 87 篇 光学工程
- 83 篇 生物工程
- 79 篇 机械工程
- 71 篇 动力工程及工程热...
- 50 篇 材料科学与工程（可...
- 43 篇 化学工程与技术
- 38 篇 生物医学工程（可授...
- 37 篇 仪器科学与技术
- 33 篇 建筑学
- 30 篇 土木工程
- 22 篇 力学（可授工学、理...
744 篇 理学
- 427 篇 物理学
- 247 篇 数学
- 96 篇 生物学
- 59 篇 统计学（可授理学、...
- 57 篇 系统科学
- 52 篇 化学
196 篇 管理学
- 147 篇 管理科学与工程(可...
- 59 篇 图书情报与档案管...
- 41 篇 工商管理
42 篇 医学
- 34 篇 临床医学
- 30 篇 基础医学(可授医学...
21 篇 法学
18 篇 经济学
10 篇 农学
6 篇 军事学
4 篇 教育学
3 篇 文学
2 篇 哲学
2 篇 艺术学

主题

111 篇 hadron colliders
75 篇 computer archite...
41 篇 laboratories
39 篇 hardware
33 篇 computational mo...
33 篇 delay
33 篇 training
31 篇 higgs bosons
29 篇 w & z bosons
29 篇 deep learning
29 篇 circuit faults
25 篇 semantics
24 篇 benchmarking
23 篇 bandwidth
23 篇 wireless sensor ...
23 篇 costs
21 篇 quantum cryptogr...
21 篇 energy efficienc...
20 篇 neural networks
20 篇 top quark

机构

208 篇 state key labora...
191 篇 yerevan physics ...
163 篇 university of ch...
151 篇 centro brasileir...
150 篇 national and kap...
150 篇 istanbul technic...
149 篇 university of sp...
148 篇 universidad iber...
148 篇 indian institute...
146 篇 brunel universit...
146 篇 academy of scien...
143 篇 charles universi...
139 篇 università di to...
136 篇 infn sezione di ...
135 篇 imperial college...
135 篇 university of de...
134 篇 rwth aachen univ...
134 篇 department of ph...
133 篇 infn sezione di ...
132 篇 indian institute...

作者

112 篇 g. tonelli
112 篇 d. barney
112 篇 l. valencia palo...
112 篇 t. liu
112 篇 c. hensel
112 篇 a. garcia-bellid...
111 篇 a. babaev
111 篇 a. steen
111 篇 n. cartiglia
108 篇 v. karjavine
105 篇 n. colino
105 篇 f. moortgat
104 篇 b. clerbaux
104 篇 g. sultanov
103 篇 m. a. ciocci
103 篇 k. lamichhane
103 篇 s. maselli
102 篇 e. migliore
102 篇 p. avery
102 篇 l. silvestris

语言

1,693 篇 英文
74 篇 中文
28 篇 其他

检索条件"机构=State Key Laboratory of Computer Architecture~ Institute of Computing Technology"

共 1791 条记录，以下是1631-1640 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Smallest Enclosing Circle Based Localization Approach for Wireless Sensor Networks

Smallest Enclosing Circle Based Localization Approach for Wi...

引用

WRI International Conference on Communications and Mobile computing, CMC

作者： Quan Zhou Xiaowei Li Yongjun Xu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Laboratory of Sensor Networks Institute of Computing Technology Chinese Academy and Sciences Beijing China

A novel range-free localization approach, smallest enclosing Circle based Localization (SECL), has been proposed. This approach uses the center of smallest enclosing circle of neighboring anchor nodes to estimate the position of target. Comparing to centroid, SECL considers the geometrical coverage of anchors rather than the mass center of them. Consequently, SECL is robust to imperfect topology, especially when the topology of anchors is depolyed unevenly. Simulation results show that SECL outperforms Centroid by an average of 10%, and even better when the topology is not uniform.

关键词： Wireless sensor networks Network topology computer networks Laboratories Robustness Computational modeling Equations Hardware Mobile communication Mobile computing

来源：评论

学校读者我要写书评

暂无评论

A self-repairable microprocessor

A self-repairable microprocessor

引用

ISTC/CSTIC 2009 (CISTC)

作者： Xie, Yuanjiang Fu, Xiang He, Zijian Zhao, Yang Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate School of Chinese Academy of Sciences Beijing 100049 China Department of Computer Science and Engineering University of California Riverside 92521 United States

ISBN: (纸本)9781615676460

With increasing defect density, microprocessors, especially the embedded caches, will encounter more faults. Adding spare resources to replace defective components is a widely accepted method for yield enhancement. In this work, a repair method using content addressable memory combined with spare bits, as well as a novel fault injection method is proposed. With the proposed fault injection technique, various numbers and types of faults can be flexibly injected into the silicon. A wireless sensor network system using our self-repairable microprocessor (SRP) is developed to prove the effectiveness of the proposed technique. ©The Electrochemical Society.

关键词： Wireless sensor networks

来源：评论

学校读者我要写书评

暂无评论

Characterizing Betweenness Centrality Algorithm on Multi-core architectures

Characterizing Betweenness Centrality Algorithm on Multi-cor...

引用

International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Dengbiao Tu Guangming Tan Chinese Academy and Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

This paper presents an in-depth analysis of characterization for an irregular application - computing betweenness centrality (BC) - on multicore architectures. BC algorithm is widely used in large scale graph analysis applications, which play an increasingly important role in high performance computing community. Through a joint study of architecture and application, we find that dynamically non-contiguous memory access, unstructured parallelism and low arithmetic intensity in BC program pose an obstacle to an efficient execution on parallel architectures. The experimental results report a comparison between Intel Clovertown and Sun Niagara1 for running such irregular program. Finally, several implications on multicore architecture and programming are proposed.

关键词： computer architecture Multicore processing computer applications Large-scale systems Performance analysis Algorithm design and analysis High performance computing Parallel processing Arithmetic Parallel architectures

来源：评论

学校读者我要写书评

暂无评论

Impact of Hazards on Pattern Selection for Small Delay Defects

Impact of Hazards on Pattern Selection for Small Delay Defec...

引用

Pacific Rim International Symposium on Dependable computing

作者： Jie Wang Huawei Li Yinghua Min Xiaowei Li Huaguo Liang School of Computer and Information Hefei University of Technology Hefei China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Hazards ubiquitously exist in combinational circuits, and then should be taken into account for delay testing. This paper analyzes the impact of hazards on small-delay defect (SDD) detection, and presents a new test pattern selection method considering hazards. The concept of arrival time window is introduced and the concept of output deviation is redefined to accurately reflect the pattern capability on SDD detection. A new signal transition probability calculation method is presented to calculate output deviation more practical than that without considering hazards. Patterns from an N-detect test set for transition faults are then selected according to their output deviations. Experimental results show that, for the same pattern count, the patterns selected by the proposed method excite more long paths, and are capable of detecting more small delay defects at the early stage of delay testing compared to the method without considering hazards.

关键词： Hazards Circuit testing Circuit faults Automatic test pattern generation Delay effects Timing Clocks Propagation delay Logic testing Crosstalk

来源：评论

学校读者我要写书评

暂无评论

A Low Overhead On-Chip Path Delay Measurement Circuit

A Low Overhead On-Chip Path Delay Measurement Circuit

引用

Asian Test Symposium (ATS)

作者： Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed method can achieve a large delay measurement range with a small quantity of delay stages. Experimental results show that a significant reduction in both delay measurement time and area overhead can be obtained compared to the previous Vernier Delay Line based delay measurement schemes. In addition, by conducting delay compensation, the proposed method can achieve both improved delay measurement resolution and measurement accuracy.

关键词： Integrated circuit measurements Delay effects Area measurement Time measurement Delay lines Electrical fault detection Fault detection Debugging Circuit faults Added delay

来源：评论

学校读者我要写书评

暂无评论

Small Delay Fault Simulation for Sequential Circuits

Small Delay Fault Simulation for Sequential Circuits

引用

Pacific Rim International Symposium on Dependable computing

作者： Li Liu Jishun Kuang Huawei Li School of Computer and Communication Hunan University Changsha China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Small-delay faults may escape detection by transition fault patterns, but traditional transition fault simulator can not detect this phenomenon. A fault simulator detecting test escape of small-delay faults is presented. The sizes of the faults are less than one system clock cycle. For our method, the delay distribution in the CUT is considered, and the fault size is quantized as times of the propagation delay in an inverter. By a waveform simulation based on Boolean process, the simulator is able to show the time interval that the fault affects and determine whether the propagation delay exceeds the system clock cycle. It might give ATPG a little of useful information.

关键词： Circuit faults Circuit simulation Sequential circuits Electrical fault detection Fault detection Propagation delay Clocks Circuit testing Inverters Automatic test pattern generation

来源：评论

学校读者我要写书评

暂无评论

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes

A New Multiple-Round DOR Routing for 2D Network-on-Chip Mesh...

引用

Pacific Rim International Symposium on Dependable computing

作者： Binzhang Fu Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

The Network-on-Chip (NoC) meshes are limited by the reliability constraint, which impels us to exploit the fault tolerant routing. Particularly, one of the main design issues is minimizing the loss of non-faulty routers at the presence of faults. To address that problem, we propose a new fault tolerant routing, which has the following two distinct advantages: First, it keeps a network deadlock-free by utilizing restricted intermediate nodes rather than adding virtual channels (VC). This characteristic leads to an area-efficient router. Second, in the proposed routing algorithm, the rounds of DOR are not limited by the number of VC's anymore. As a consequence, the number of sacrificed non-faulty routers is significantly reduced. We demonstrate above advantages through extensive simulations. The experimental results show that under the limitation of VC's, the proposed routing algorithm always sacrifices the minimal number of non-faulty routers compared to previous solutions.

关键词： Routing Network-on-a-chip Virtual colonoscopy Fault tolerance System recovery computer networks Region 4 Shape Laboratories computer architecture

来源：评论

学校读者我要写书评

暂无评论

Efficient Physical Design Methodology for Reducing Test Power Dissipation of Scan-Based Designs

Efficient Physical Design Methodology for Reducing Test Powe...

引用

International Conference on Networking, architecture, and Storage (NAS)

作者： Jun Xu Xiangku Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing China

Scan-based test methodology is used to resolve the sequential-test problem but suffers from high power dissipation. In this paper, we propose a scheme to prevent transitions of scan chain from reflecting into the circuit line. It not only can save 23% power consumption without performance loss, but also can be easily implemented with popular industrial design tools.

关键词： Design methodology Power dissipation Circuit testing Automatic test pattern generation Sequential analysis Registers computer architecture System testing Logic Controllability

来源：评论

学校读者我要写书评

暂无评论

A Scalable Scan architecture for Godson-3 Multicore Microprocessor

A Scalable Scan Architecture for Godson-3 Multicore Micropro...

引用

Asian Test Symposium (ATS)

作者： Zichu Qi Hui Liu Xiangku Li Da Wang Yinhe Han Huawei Li Weiwu Hu Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (scalable mesh of crossbar) on-chip network and targets high-end applications. Advanced techniques are adopted to achieve the scalable, low-power and low-cost scan architecture at the challenge of limited I/O resources and large scale of transistors. To achieve a scalable and flexible test access, a highly elaborate TAM (test access mechanism) is implemented with supporting multiple test instructions and test modes. Taking advantage of multiple cores embedding in the processor, scan partitions are employed to reduce test power and test time, and test compression with more than 10X compression ratio are utilized to decrease the scan chain length. To further decrease test time, a data-synchronous-comparator (DSC) is proposed for comparing the scan responses of the identical cores.

关键词： Multicore processing Microprocessors Switches computer architecture System testing Laboratories Large-scale systems Linear predictive coding Delay Logic testing

来源：评论

学校读者我要写书评

暂无评论

A Low-Complexity Synchronization Based Cache Coherence Solution for Many Cores

A Low-Complexity Synchronization Based Cache Coherence Solut...

引用

International Conference on computer and Information technology (CIT)

作者： Wei Lin DongRui Fan He Huang Nan Yuan XiaoChun Ye Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

computer architectures make a dramatic turn away from improving single-processor performance towards improved parallel performance through integrating many cores in one chip. However, providing directory based coherence protocols for these platforms is too complex and expensive. As a substitute, we propose a synchronization based cache coherence solution, which uses different cache policies according to three flexible software guided scopes (exclusion, producer and consumer scopes) to solve the data-race and coherence problem. Furthermore, this protocol implements word dirty bits (only one bit per word is needed in each L1 cache line) and a special hardware synchronization manager (HSM) to support multi-writer, the write-validate policy and to eliminate the remote un-cache spinning at the ldquoflagrdquo. We evaluate Godson-T, a platform supporting this protocol, against an idealized interleaved dual tag directory based protocol on the Splash2 and two bioinformatics benchmarks. The performance of the synch-based protocol is degraded only at 3.2% on average, but the real chip area is reduced at 32% even if the overhead of HSM is included.

关键词： Protocols computer architecture Hardware Concurrent computing Costs Network-on-a-chip Coherence Tiles Information technology Helium

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共180页 << < 160 161 162 163 164 165 166 167 168 169 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：