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检索条件"机构=State Key Laboratory of Computer Architecture~ Institute of Computing Technology"
1773 条 记 录,以下是1631-1640 订阅
排序:
A Scalable Scan architecture for Godson-3 Multicore Microprocessor
A Scalable Scan Architecture for Godson-3 Multicore Micropro...
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Asian Test Symposium (ATS)
作者: Zichu Qi Hui Liu Xiangku Li Da Wang Yinhe Han Huawei Li Weiwu Hu Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (scalable mesh of crossbar) on-chip network and targets high-... 详细信息
来源: 评论
A Low-Complexity Synchronization Based Cache Coherence Solution for Many Cores
A Low-Complexity Synchronization Based Cache Coherence Solut...
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International Conference on computer and Information technology (CIT)
作者: Wei Lin DongRui Fan He Huang Nan Yuan XiaoChun Ye Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
computer architectures make a dramatic turn away from improving single-processor performance towards improved parallel performance through integrating many cores in one chip. However, providing directory based coheren... 详细信息
来源: 评论
Online computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures
Online Computing and Predicting Architectural Vulnerability ...
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Pacific Rim International Symposium on Dependable computing
作者: Songjun Pan Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Soft Errors have emerged as a key challenge to microprocessor design. Traditional soft error tolerance techniques (such as redundant multithreading and instruction duplication) can achieve high fault coverage but at t... 详细信息
来源: 评论
Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy
Variation-Aware Scheduling for Chip Multiprocessors with Thr...
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Pacific Rim International Symposium on Dependable computing
作者: Jianbo Dong Lei Zhang Yinhe Han Guihai Yan Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Thread-level redundancy in Chip Multiprocessors(TLR-CMP) is efficient for soft error tolerance. Process variation causes core-to-core (C2C) performance asymmetry across a chip, which should be taken into consideration... 详细信息
来源: 评论
Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan
Flip-Flop Selection for Transition Test Pattern Reduction Us...
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Pacific Rim International Symposium on Dependable computing
作者: Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Enhanced scan delay testing approach can achieve high transition delay fault coverage by a small size of test pattern set but with significant hardware overhead. Although the implementation cost of launch on capture (... 详细信息
来源: 评论
Design of New Hash Mapping Functions
Design of New Hash Mapping Functions
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International Conference on computer and Information technology (CIT)
作者: Fenglong Song Zhiyong Liu Dongrui Fan Junchao Zhang Lei Yu Nan Yuan Wei Lin Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Conflict can decrease performance of computer severely, such as bank conflicts reduce bandwidth of interleave multibank memory systems and conflict misses reduce effective on-chip capacity, and this incurs much confli... 详细信息
来源: 评论
Evaluation Method of Synchronization for Shared-Memory On-Chip Many-Core Processor
Evaluation Method of Synchronization for Shared-Memory On-Ch...
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International Symposium on Parallel and Distributed Processing with Applications, ISPA
作者: Fenglong Song Zhiyong Liu Dongrui Fan He Huang Nan Yuan Lei Yu Junchao Zhang Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
On-chip many core architecture is an emerging and promising computation platform. High speed on-chip communication and abundant chipped resources are two outstanding advantages of this architecture, which provide an o... 详细信息
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Study on Fine-Grained Synchronization in Many-Core architecture
Study on Fine-Grained Synchronization in Many-Core Architect...
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ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed computing (SNPD)
作者: Lei Yu Zhiyong Liu Dongrui Fan Fenglong Song Junchao Zhang Nan Yuan Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
The synchronization between threads has serious impact on the performance of many-core architecture. When communication is frequent, coarse-grained synchronization brings significant overhead. Thus, coarse-grained syn... 详细信息
来源: 评论
Data Management: The Spirit to Pursuit Peak Performance on Many-Core Processor
Data Management: The Spirit to Pursuit Peak Performance on M...
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International Symposium on Parallel and Distributed Processing with Applications, ISPA
作者: Yongbin Zhou Junchao Zhang Shuai Zhang Nan Yuan Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN
To date, most of many-core prototypes employ tiled topologies connected through on-chip networks. The throughput and latency of the on-chip networks usually become to the bottleneck to achieve peak performance especia... 详细信息
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A case study of improving at-speed testing coverage of a gigahertz microprocessor
A case study of improving at-speed testing coverage of a gig...
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IEEE International Conference on Electronics, Circuits and Systems (ICECS)
作者: Zichu Qi Hui Liu Xiangku Li Jun Xu Weiwu Hu Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
For a gigahertz microprocessor with multiple clock domains and a large amount of embedded RAMs (random access memory), generating at-speed testing patterns is becoming very difficult and very time-consuming. This pape... 详细信息
来源: 评论