检索结果-内蒙古大学图书馆

International Symposium on Knowledge Acquisition and Modeling, KAM

作者： Shaoran Dong Zengzhi Li State key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications Beijing China Institute of Computer System Architecture and Network Xi''an Jiaotong University Xi'an China

To analyze model of Web services composition, firstly analyze and abstract dataflow and control construct in OWL-S process to build high level Petri net model, then describe Petri net in Poses++ language, at last simulate Petri net with Poses++ to check data type and deadlock and calculate service performance. The experiment shows that this model analyzing method is able to accomplish type checking and deadlock and performance analyzing.

关键词： Performance analysis Web services System recovery Data analysis Petri nets Ontologies OWL Analytical models Knowledge acquisition computer networks

来源：评论

学校读者我要写书评

暂无评论

Particle Swarm Algorithm for the Quality of Service-Oriented Web Services Selection

Particle Swarm Algorithm for the Quality of Service-Oriented...

引用

International Symposium on Knowledge Acquisition and Modeling, KAM

作者： Hong Xia Zengzhi Li State key Laboratory of Networking and Switch Technology Beijing University of Posts and Telecommunications Beijing China Institute of Computer System Architecture and Network Xi''an Jiaotong University Xi'an Shaanxi China

Existing Web services composition technology, lack of services selecting. A particle swarm optimization algorithm based on the multi-objective optimization strategies was provided to address quality of services to choose the issue of global optimization. It is to transform Web services select the overall optimization problem with QoS into a multi-objective constrained optimization problem based on Qos, using multi-objective PSO intelligent theory, by a number of Qos parameters optimized at the same time, and ultimately produce a set of constraints to meet the Pareto optimal solution. The experimental results show the feasibility and efficiency of the algorithm.

关键词： Particle swarm optimization Web services Quality of service Constraint optimization Pareto optimization Service oriented architecture Switches Constraint theory Logic Optimization methods

来源：评论

学校读者我要写书评

暂无评论

Verification Web Services Composition Based on OWL-S

Verification Web Services Composition Based on OWL-S

引用

International Symposium on Knowledge Acquisition and Modeling, KAM

In order to ensure the correctness and reliability of Web services composition based on OWL-S, verify the interaction protocol of Web services. It is provided that three lay architecture. Composition service based on OWL-S, GA model is the middle model and the Promela model is the verification model, SPIN as a model validator. The OWL-S composition Web services transform a top-down conversation protocol process into a GA model, use WAST tool into Promela model, the SPIN tool analysis and verification structure and performance of composition services. This method is flexibility and scalability which provide a solution for Web services composition model verification.

关键词： Web services XML Protocols state-space methods Scalability Service oriented architecture computer architecture Switches Automata Asynchronous communication

来源：评论

学校读者我要写书评

暂无评论

Automated Design of Logic Circuits with a Increasable Evolution Approach

Automated Design of Logic Circuits with a Increasable Evolut...

引用

IEEE International Conference on High Performance computing and Communications (HPCC)

作者： Guoliang He Naixue Xiong Athanasios V. Vasilakos Yuanxiang Li Zhongzhi Shi State Key Laboratory of Software Engineering Wuhan University of China Wuhan China Key Laboratory of Intelligent Information Process Institute of Computing Technology Chinese Academy and Sciences Beijing China Department of Computer Science Georgia State University USA Department of Computer Science Saint Francis Xavier University Canada

Since the scalability of logic circuits is becoming larger and more complex, the auto-design is becoming more and more difficult. In order to improve automatic design and performance evaluation of logic circuits in efficiency and capability of optimization, multiobjective simulated annealing (MSA) based increasable evolution approach is designed to evolve logic circuits automatically with an extended matrix encoding method, which can be able to reflect the potential performance of a circuit and reduce the risk of deleting a circuit with a good developing potential during evolution is devised. In the process of evolution, each individual is renewedly associated to a corresponding objective in terms of a novel adaptive evaluation method at each generation. In experiments, complicated arithmetic circuits are designed to assess the performance of MSA against other algorithms. Results indicate that the proposed method could design logic circuits efficiently.

关键词： Logic circuits Encoding Hardware Scalability Circuit simulation Simulated annealing Genetic algorithms Laboratories computer science Arithmetic

来源：评论

学校读者我要写书评

暂无评论

Energy Efficient TDMA Sleep Scheduling in Wireless Sensor Networks

Energy Efficient TDMA Sleep Scheduling in Wireless Sensor Ne...

引用

IEEE Annual Joint Conference: INFOCOM, IEEE computer and Communications Societies

作者： J. Ma W. Lou Y. Wu X.-Y. Li G. Chen Department of Computing Hong Kong Polytechnic University Hong Kong China Department of Computer Science Illinois Institute of Technology IL USA State Key Laboratory of Novel Software Technology Nanjing University Nanjing China

ISBN: (纸本)9781424435128

Sleep scheduling is a widely used mechanism in wireless sensor networks (WSNs) to reduce the energy consumption since it can save the energy wastage caused by the idle listening state. In a traditional sleep scheduling, however, sensors have to start up numerous times in a period, and thus consume extra energy due to the state transitions. The objective of this paper is to design an energy efficient sleep scheduling for low data-rate WSNs, where sensors not only consume different amounts of energy in different states (transmit, receive, idle and sleep), but also consume energy for state transitions. We use TDMA as the MAC layer protocol, because it has the advantages of avoiding collisions, idle listening and overhearing. We first propose a novel interference-free TDMA sleep scheduling problem called contiguous link scheduling, which assigns sensors with consecutive time slots to reduce the frequency of state transitions. To tackle this problem, we then present efficient centralized and distributed algorithms that use time slots at most a constant factor of the optimum. The simulation studies corroborate the theoretical results, and show the efficiency of our proposed algorithms.

关键词： Energy efficiency Time division multiple access Sleep Wireless sensor networks Interference Energy consumption Delay Processor scheduling Media Access Protocol Frequency

来源：评论

学校读者我要写书评

暂无评论

Design of a flip-flop circuit within digital logic analyzer based on FPGA

引用

Harbin Gongye Daxue Xuebao/Journal of Harbin institute of technology 2009年第SUPPL. 1期41卷 58-62页

作者： Xiao, Ling-Li Xu, Ning Han, Yin-He School of Computer Science and Technology Wuhan University Of Technology Wuhan 430070 China System Architecture Key Laboratory Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

With the wide application of EDA technique, the period for the development of electronic products has been shortened. That implements the software of the hardware design and reduces the costs. Based on the analysis of the principle of digital logic analyzer circuit, this paper discusses the working principles of its flip-flop circuit module and the implementation method of FPGA, and presents the program design and emulation result of part circuits.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

A parallel optimization model for massive data stream application

引用

Ruan Jian Xue Bao/Journal of Software 2009年第SUPPL. 1期20卷 23-33页

作者： Sun, Xiao-Juan Sun, Ning-Hui Lei, Bin Key Laboratory of Technology in Geo-Spatial Information Processing and Application System Institute of Electronics The Chinese Academy of Sciences Beijing 100190 China Key Laboratory of Computer System and Architecture Institute of Computing Technology The Chinese Academy of Sciences Beijing 100190 China

While computing is entering a new phase in which CPU improvements are driven by the addition of multiple cores on a single chip, rather than higher frequencies. Parallel processing on these systems is in a primitive stage, and requires the explicit use and knowledge of underlying thread architecture. Based on the features of massive data stream application, this paper proposes three-level pipelining programming model of multithreading system, which realizes the new synchronization mechanism with no contention of shared structures and is capable to provide differential service for data streams. Then the paper applies the new model to remote sensing information processing system and backbone network intrusion detection system, and evaluates the improved system on several multicore platforms. In performance analysis, the optimized effects of backbone network intrusion detection system are evaluated in several aspects of throughput scalability on both SPARC T1 and x86 platforms, the impacts of different multithreading mapping methods on throughput, and the comparison of response time and service quality before and after optimization. The experimental results show that the system throughput has good scalability on both platforms, the values of response time are greatly improved and the prioritized streams achieve better response time with the differential service mechanism. © by institute of Software, the Chinese Academy of Sciences. All rights reserved.

关键词： Metadata

来源：评论

学校读者我要写书评

暂无评论

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

引用

Journal of computer Science & technology 2008年第6期23卷 1037-1046页

作者：王达胡瑜李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences

This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test （BIST） circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops （PLL） to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation （ATPG） and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing （HVM） DFT plan to meet high quality test goals as well as slow test power consumption and cost.

关键词： microprocessor design-for-testability test generation built-in self-test at-speed testing

来源：评论

学校读者我要写书评

暂无评论

Register pressure sensitive instruction speculative scheduling technology

引用

Jisuanji Yanjiu yu Fazhan/computer Research and Development 2009年第3期46卷 485-491页

作者： Huang, Lei Feng, Xiaobing Lü, Fang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

Speculation is an important method to overcome control flow constraints during instruction scheduling. On the one hand, speculation can exploit more instruction-level parallelism and improve performance. However, on the other hand, it may also lengthen the live range of variables and increase the register pressure, which in turn results in spilling some variables to memory and deteriorating the performance. Previous work on register pressure sensitive instruction scheduling generally scheduled instructions conservatively when there were too many live variables in the scheduling region. But actually different variables have different spilling costs and different impacts on performance. Here a register pressure sensitive speculative instruction scheduling technology is presented, which not only considers the count of live variables, but also analyzes the benefits and the spilling costs brought by instructions' speculative motions. The decrement of cycles in critical path is calculated as benefit, while the spilled variables are predicted and their spilling cost is used as cost. Only the speculative motion with benefit greater than the cost is permitted in our method. This algorithm has been implemented in Godson Compiler for MIPS architecture. Experiment result shows that the method in this paper can obtain 1.44% speedup on average relative to its register pressure insensitive counterpart on SPEC CPU2000INT benchmarks.

关键词： Costs

来源：评论

学校读者我要写书评

暂无评论

Tradeoff cache between latency and capacity in chip multiprocessors

引用

Jisuanji Yanjiu yu Fazhan/computer Research and Development 2009年第1期46卷 167-175页

作者： Xiao, Junhua Feng, Zijun Zhang, Longbing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate School Chinese Academy of Sciences Beijing 100049 China

Chip multiprocessors (CMP) have become the main stream microprocessor architecture. In CMP, the cache, especially the last level cache, is the critical part of its performance and becomes a focus of current research activities. CMP cache faces the conflicting requirements of satisfying both latency and capacity, and has to trade off between techniques that reduce off-chip and cross-chip misses. The private cache design minimizes the cache access latency but reduces the total effective cache capacity. The shared cache design maximizes the effective cache capacity but incurs long hit latency. In this paper, a CMP cache design (tradeoff cache between latency and capacity, TCLC) is proposed. TCLC is a private and shared hybrid design. TCLC can dynamically identify the cache blocks' shared type and optimize them respectively. The private type is optimized through migration policy, the shared read-only type is optimized through replication policy, and the shared read-write type is optimized through center placement policy. TCLC tries to make cache access latency close to private design, and effective cache capacity close to shared design, which can mitigate the impact of the wire delay and reduce the average memory access latency. The experiment results indicate that this proposal performs 13.7% better than a private cache and 12% better than a shared cache.

关键词： Economic and social effects

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：