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A Survey of Non-Volatile Main Memory File Systems

Journal of computer Science & technology 2023年第2期38卷 348-372页

作者：王盈贾文庆蒋德钧熊劲 State Key Laboratory of Processors Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China Research Center for Advanced Computer Systems Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China

Non-volatile memories(NVMs)provide lower latency and higher bandwidth than block ***,NVMs are byte-addressable and provide persistence that can be used as memory-level storage devices(non-volatile main memory,NVMM).These features change storage hierarchy and allow CPU to access persistent data using load/store ***,we can directly build a file system on ***,traditional file systems are designed based on slow block *** use a deep and complex software stack to optimize file system *** design results in software overhead being the dominant factor affecting NVMM file ***,scalability,crash consistency,data protection,and cross-media storage should be reconsidered in NVMM file *** survey existing work on optimizing NVMM file ***,we analyze the problems when directly using traditional file systems on NVMM,including heavy software overhead,limited scalability,inappropriate consistency guarantee techniques,***,we summarize the technique of 30 typical NVMM file systems and analyze their advantages and ***,we provide a few suggestions for designing a high-performance NVMM file system based on real hardware Optane DC persistent memory ***,we suggest applying various techniques to reduce software overheads,improving the scalability of virtual file system(VFS),adopting highly-concurrent data structures(e.g.,lock and index),using memory protection keys(MPK)for data protection,and carefully designing data placement/migration for cross-media file system.

关键词： non-volatile main memory(NVMM) file system performance scalability crash consistency data protection crossmeida

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The rise of high-throughput computing

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Frontiers of Information technology & Electronic Engineering 2018年第10期19卷 1245-1250页

作者： Ning-hui SUN Yun-gang BAO Dong-rui FAN State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesUniversity of Chinese Academy of Sciences

In recent years, the advent of emerging computing applications, such as cloud computing, artificial intelligence, and the Internet of Things, has led to three common requirements in computer system design： high utilization, high throughput, and low latency. Herein, these are referred to as the requirements of ＇high-throughput computing （HTC）＇. We further propose a new indicator called ＇sysentropy＇ for measuring the degree of chaos and uncertainty within a computer system. We argue that unlike the designs of traditional computing systems that pursue high performance and low power consumption, HTC should aim at achieving low sysentropy. However, from the perspective of computer architecture, HTC faces two major challenges that relate to （1） the full exploitation of the application＇s data parallelism and execution concurrency to achieve high throughput, and （2） the achievement of low latency, even in the cases at which severe contention occurs in data paths with high utilization. To overcome these two challenges, we introduce two techniques： on-chip data flow architecture and labeled von Neumann architecture. We build two prototypes that can achieve high throughput and low latency, thereby significantly reducing sysentropy.

关键词： High-throughput computing Sysentropy Information superbahn

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Parallel Error Detection for Leading Zero Anticipation

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Journal of computer Science & technology 2006年第6期21卷 901-906页

作者：张戈胡伟武齐子初 Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 P.R. China Graduate University of the Chinese Academy of Sciences Beijing 100039 P.R. China

The algorithm and its implementation of the leading zero anticipation （LZA） are very vital for the performance of a high-speed floating-point adder in today＇s state of art microprocessor design. Unfortunately, in predicting ＂shift amount＂ by a conventional LZA design, the result could be off by one position. This paper presents a novel parallel error detection algorithm for a general-case LZA. The proposed approach enables parallel execution of conventional LZA and its error detection, so that the error-indicatlon signal can be generated earlier in the stage of normalization, thus reducing the critical path and improving overall performance. The circuit implementation of this algorithm also shows its advantages of area and power compared with other previous work.

关键词： computer arithmetic floating-point addition leading zero anticipation

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Fast and efficient parallel breadth-first search with power-law graph transformation

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Frontiers of computer Science 2022年第5期16卷 225-227页

作者： Zite JIANG Tao LIU Shuai ZHANG Mengting YUAN Haihang YOU School of Computer Science and Technology University of Chinese Academy of SciencesBeijing 100049China State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China School of Comptuer Science Wuhan UniversityWuhan 430072China

1 Introduction Most real-world graphs are large-scale but unstructured and *** of the most notable characteristics of real-world graphs is the skewed power law degree distribution[1]:most vertices have a few neighbors while a few own a large number of *** characteristics present challenges for efficient parallel graph processing,such as load imbalance,poor locality,and redundant *** from modifying the graph programming abstraction or changing the execution models on different architectures,reducing the irregularity of graph data also improves the performance of graph processing[2].For example,it is wellknown that BFS has a bad temporal locality,but it is possible to transform irregular graphs to more regular ones to improve spatial locality and gain more performance.

关键词： neighbor programming redundant

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A parallel algorithm for computing betweenness centrality

A parallel algorithm for computing betweenness centrality

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38th International Conference on Parallel Processing, ICPP-2009

作者： Tan, Guangming Tu, Dengbiao Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China

ISBN: (纸本)9780769538020

In this paper we present a multi-grained parallel algorithm for computing betweenness centrality, which is extensively used in large-scale network analysis. Our method is based on a novel algorithmic handling of access conflicts for a CREW PRAM algorithm. We propose a proper data-processor mapping, a novel edge-numbering strategy and a new triple array data structure recording the shortest path for eliminating conflicts to access the shared memory. The algorithm requires O(n + m) space and O(nm/p ) ( or O(nm+n2logn /p )) time for unweighted (or weighted) graphs, and it is a work-optimal CREW PRAM algorithm. On current multi-core platforms, our algorithm outperforms the previous algorithm by 2-3 times. © 2009 IEEE.

关键词： Parallel algorithms

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Software and hardware cooperate for 1-D FFT algorithm optimization on multicore processors

Software and hardware cooperate for 1-D FFT algorithm optimi...

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IEEE 9th International Conference on computer and Information technology, CIT 2009

作者： Zhou, Yongbin Zhang, Junchao Fan, Dongrui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

Multicore architecture is becoming a promise to keep Moore's Law and brings a revolution in both research and industry which results new design space for software and architecture. Fast Fourier Transform (FFT), computing intensive and bandwidth intensive, is one of the most popular and important applications in the world. Compared with the computing resource on multicore architecture, the on-chip memory resource is much more expensive because of the limitation of physical chip size. Efficient implementation of FFT algorithm on multicore with good scalability is a challenge for both software and hardware developers. In this paper, supported by the Godson-T architecture, an optimized implementation of 1-D FFT has been developed with matrix transpose conceal and computation/communication overlapping, which achieve more than 30% performance improvement as well as almost 1/3 L2 cache consumption reduce comparing with the base six-step FFT. The limitation of scalability is also analyzed and the conclusion is that on Godson-T when frequency and simultaneous data access happen, the limited access bandwidth of L2 cache is the bottleneck and result in the longer on-chip network latency. © 2009 IEEE.

关键词： Fast Fourier transforms

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Circuit implementation of floating point range reduction for trigonometric functions

Circuit implementation of floating point range reduction for...

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2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007

作者： Xuehai, Qian Hao, Zhang Jingang, Yang He, Huang Junchao, Zhang Dongrui, Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Range reduction is important in evaluating trigonometric functions but not enough work is done in relation to the hardware implementation of it. A hardware floating point range reduction implementation is presented. The whole reduction is divided into two steps;the first is based on Double-Residue modular range reduction method and the second adopts on a novel method described in this paper. The latter one can reduce the argument to an arbitrary range and provides the number of times that range constant contained in the argument It has been synthesized using 0.13 um library to achieve an approximately 700 MHz operation frequency. © 2007 IEEE.

关键词： Digital circuits

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Snooping and ordering ring - An efficient cache coherence protocol for ring connected CMP

Snooping and ordering ring - An efficient cache coherence pr...

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15th International Conference on Parallel and Distributed Systems, ICPADS '09

作者： Cao, Fei Liu, Zhiyong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China

ISBN: (纸本)9780769539003

Ring is a promising on-chip interconnection for CMP. It is more scalable than bus and much simpler than packet-switched networks. The ordering property of ring can be used to optimize cache coherence protocol design. Existing ring protocols, such as the snooping ring protocol and the ring-order protocol need a retry and acknowledgement scheme or use the ordering property of the ring respectively to resolve conflict memory requests. A cache coherence protocol named SOR (Snooping and Ordering Ring) is developed for ring connected CMP in this paper. This protocol is based on the snooping ring protocol. But instead of using the acknowledgement and retry scheme, it uses the ordering property of the ring to resolve conflicts, thus can avoid unnecessary retries to improve performance and power efficiency. The L1 snooping results are sent with the requests instead of being delayed, so that many useless snoops can be avoided. Simulation result shows that the average probe slot transports and snoop operations can be reduced by SOR are 47% and 48.9%. The average and maximum performance improvements by SOR are 3.33% and 6%. © 2009 IEEE.

关键词： Packet switching

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Diff9D: Diffusion-Based Domain-Generalized Category-Level 9-DoF Object Pose Estimation

arXiv

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arXiv 2025年

作者： Liu, Jian Sun, Wei Yang, Hui Deng, Pengchao Liu, Chongpei Sebe, Nicu Rahmani, Hossein Mian, Ajmal National Engineering Research Center for Robot Visual Perception and Control Technology College of Electrical and Information Engineering School of Robotics State Key Laboratory of Advanced Design and Manufacturing for Vehicle Body Hunan University Changsha410082 China Institute of Artificial Intelligence and Robotics Xi’an Jiaotong University Xi’an710049 China Department of Information Engineering and Computer Science University of Trento Trento38123 Italy School of Computing and Communications Lancaster University LA1 4YW United Kingdom Department of Computer Science The University of Western Australia WA6009 Australia

Nine-degrees-of-freedom (9-DoF) object pose and size estimation is crucial for enabling augmented reality and robotic manipulation. Category-level methods have received extensive research attention due to their potential for generalization to intra-class unknown objects. However, these methods require manual collection and labeling of large-scale real-world training data. To address this problem, we introduce a diffusion-based paradigm for domain-generalized category-level 9-DoF object pose estimation. Our motivation is to leverage the latent generalization ability of the diffusion model to address the domain generalization challenge in object pose estimation. This entails training the model exclusively on rendered synthetic data to achieve generalization to real-world scenes. We propose an effective diffusion model to redefine 9-DoF object pose estimation from a generative perspective. Our model does not require any 3D shape priors during training or inference. By employing the Denoising Diffusion Implicit Model, we demonstrate that the reverse diffusion process can be executed in as few as 3 steps, achieving near real-time performance. Finally, we design a robotic grasping system comprising both hardware and software components. Through comprehensive experiments on two benchmark datasets and the real-world robotic system, we show that our method achieves state-of-the-art domain generalization performance. Our code will be made public at https://***/CNJianLiu/Diff9D. Copyright © 2025, The Authors. All rights reserved.

关键词： Augmented reality

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A method of stub generation for I/O functions in automatic test

A method of stub generation for I/O functions in automatic t...

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International Conference on Multimedia, Communication and computing Application, MCCA 2014

作者： Yang, Y.W. Wang, Y.W. Gong, Y.Z. Wang, Y.W. State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781138027756

Library functions and system calls have been major difficulties faced by automatic test. Input/ output (I/O) functions are a set of common library functions. Testers have to interact with the test procedures if the test program contains I/O functions, resulting in inefficient automatic test. Unlike normal functions, the association between I/O functions and operating on a specific I/O device makes ordinary stub method disabled. Aiming at solving this problem, this paper proposes one solution by I/O device modeling and I/O function modeling. The semantics of the I/O functions are stored in the I/O function model, and the operations of I/O functions are similar to the I/O device model. The final state and properties of the I/O device are represented by two models. Finally the stub code is automatically generated by path-oriented stub generation technology. Experiments show that this method is effective. © 2015 Taylor & Francis Group, London.

关键词： Semantics

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