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International Conference on Multimedia, Communication and computing Application, MCCA 2014

作者： Song, H. Wang, Y.W. Qian, G.N. Gong, Y.Z. Wang, Y.W. State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781138027756

Fault injection plays a critical role in the verification of software’s reliability. This paper presents a fault injection method by mutation. Moreover, a strategy of using semantic-based mutators is proposed to improve the efficiency of mutation testing. We implemented the method in FIT, an automatic fault injection tool. Experiments prove that the method is effective and the tool can produce lots of mutants which show that mutation testing is satisfying. © 2015 Taylor & Francis Group, London.

关键词： Semantics

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piRT-IFC:Physics-informed real-time impedance flow cytometry for the characterization of cellular intrinsic electrical properties

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Microsystems & Nanoengineering 2023年第3期9卷 347-356页

作者： Xiaofeng Luan Pengbin Liu Di Huang Haiping Zhao Yuang Li Sheng Sun Wenchang Zhang Lingqian Zhang Mingxiao Li Tian Zhi Yang Zhao Chengjun Huang Institute of Microelectronics of the Chinese Academy of Sciences BeijingChina University of Chinese Academy of Sciences BeijingChina State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijingChina Cerebrovascular Diseases Research Institute Xuanwu Hospital of Capital Medical UniversityBeijingChina

Real-time transformation was important for the practical implementation of impedance flow *** major obstacle was the time-consuming step of translating raw data to cellular intrinsic electrical properties(e.g.,specific membrane capacitance C_(sm) and cytoplasm conductivityσ_(cyto)).Although optimization strategies such as neural network-aided strategies were recently reported to provide an impressive boost to the translation process,simultaneously achieving high speed,accuracy,and generalization capability is still *** this end,we proposed a fast parallel physical fitting solver that could characterize single cells’C_(sm)andσ_(cyto)within 0.62 ms/cell without any data preacquisition or pretraining *** achieved the 27000-fold acceleration without loss of accuracy compared with the traditional *** on the solver,we implemented physics-informed real-time impedance flow cytometry(piRT-IFC),which was able to characterize up to 100,902 cells’C_(sm) andσ_(cyto)within 50 min in a real-time *** to the fully connected neural network(FCNN)predictor,the proposed real-time solver showed comparable processing speed but higher ***,we used a neutrophil degranulation cell model to represent tasks to test unfamiliar samples without data for *** being treated with cytochalasin B and N-Formyl-Met-Leu-Phe,HL-60 cells underwent dynamic degranulation processes,and we characterized cell’s C_(sm)andσ_(cyto)using *** to the results from our solver,accuracy loss was observed in the results predicted by the FCNN,revealing the advantages of high speed,accuracy,and generalizability of the proposed piRT-IFC.

关键词： impedance intrinsic flow

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Tetris:A Heuristic Static Memory Management Framework for Uniform Memory Multicore Neural Network Accelerators

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Journal of computer Science & technology 2022年第6期37卷 1255-1270页

作者： Xiao-Bing Chen Hao Qi Shao-Hui Peng Yi-Min Zhuang Tian Zhi Yun-Ji Chen Distinguished Member,CCF State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China University of Chinese Academy of Sciences Beijing 100049China School of Computer Science and Technology University of Science and Technology of ChinaHeFei230026China Chinese Academy of Sciences Center for Excellence in Brain Science and Intelligence Technology Shanghai200031China 不详

Uniform memory multicore neural network accelerators(UNNAs)furnish huge computing power to emerging neural network ***,with neural network architectures going deeper and wider,the limited memory capacity has become a constraint to deploy models on UNNA *** how to efficiently manage memory space and how to reduce workload footprints are urgently *** this paper,we propose Tetris:a heuristic static memory management framework for UNNA *** reconstructs execution flows and synchronization relationships among cores to analyze each tensor’s liveness *** the memory management problem is converted to a sequence permutation *** uses a genetic algorithm to explore the permutation space to optimize the memory management strategy and reduce memory *** evaluate several typical neural networks and the experimental results demonstrate that Tetris outperforms the state-of-the-art memory allocation methods,and achieves an average memory reduction ratio of 91.9%and 87.9%for a quad-core and a 16-core Cambricon-X platform,respectively.

关键词： multicore neural network accelerators liveness analysis static memory management memory reuse genetic algorithm

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Adapting Memory Hierarchies for Emerging Datacenter Interconnects

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Journal of computer Science & technology 2015年第1期30卷 97-109页

作者：江涛侯锐董建波柴琳 Sally A. McKee 田斌张立新孙凝晖 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China Computer Science and Engineering Chalmers University of Technology Gothenburg 41296 Sweden National High Performance Integrated Circuit Design Center (Shanghai) Shanghai 201204 China

Efficient resource utilization requires that emerging datacenter interconnects support both high performance communication and efficient remote resource sharing. These goals require that the network be more tightly coupled with the CPU chips. Designing a new interconnection technology thus requires considering not only the interconnection itself, but also the design of the processors that will rely on it. In this paper, we study memory hierarchy implications for the design of high-speed datacenter interconnects particularly as they affect remote memory access -- and we use PCIe as the vehicle for our investigations. To that end, we build three complementary platforms： a PCIe-interconnected prototype server with which we measure and analyze current bottlenecks; a software simulator that lets us model microarchitectural and cache hierarchy changes; and an FPGA prototype system with a streamlined switchless customized protocol Thunder with which we study hardware optimizations outside the processor. We highlight several architectural modifications to better support remote memory access and communication, and quantify their impact and ]imitations.

关键词： high-speed interconnect memory hierarchy time shared memory datacenter network

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Statistical static timing analysis for circuit aging prediction

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The Journal of China Universities of Posts and Telecommunications 2021年第2期28卷 14-23页

作者： Duan Shengyu Zhai Dongyao Lu Yue Shanghai Engineering Research Center of Intelligent Computing System Shanghai UniversityShanghai 200444China State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China School of Electronics and Computer Science University of SouthamptonSouthamptonUK

Complementary metal oxide semiconductor(CMOS)aging mechanisms including bias temperature instability(BTI)pose growing concerns about circuit *** results in threshold voltage increases on CMOS transistors,causing delay shifts and timing violations on logic *** amount of degradation is dependent on the circuit workload,which increases the challenge for accurate BTI aging prediction at the design *** this paper,a BTI prediction method for logic circuits based on statistical static timing analysis(SSTA)is proposed,especially considering the correlation between circuit workload and BTI *** consists of a training phase,to discover the relationship between circuit scale and the required workload samples,and a prediction phase,to present the degradations under different workloads in Gaussian probability *** method can predict the distribution of degradations with negligible errors,and identify 50%more BTI-critical paths in an affordable time,compared with conventional methods.

关键词： bias temperature instability(BTI) reliability prediction statistical static timing analysis(SSTA)

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Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology

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Journal of computer Science & technology 2007年第1期22卷 1-14页

作者：胡伟武赵继业钟石强杨旭 Elio Guidetti 吴永强 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China ST Microelectronics 39 Chemin du Camp-des-Filles 1228 Plan Les Ouates Geneva Switzerland

This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bitsliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.

关键词： general-purpose processor superscalar pipeline out-of-order execution non-blocking cache physical design,synthesis flow bit-sliced placement crafted cell performance evaluation

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A Case for Adaptive Resource Management in Alibaba Datacenter Using Neural Networks

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Journal of computer Science & technology 2020年第1期35卷 209-220页

作者： Sa Wang Yan-Hai Zhu Shan-Pei Chen Tian-Ze Wu Wen-Jie Li Xu-Sheng Zhan Hai-Yang Ding Wei-Song Shi Yun-Gang Bao State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China Peng Cheng Laboratory Shenzhen 518055China Alibaba Inc. Hangzhou 311121China Department of Computer Science Wayne State UniversityMichiganMI 48202U.S.A

Both resource efficiency and application QoS have been big concerns of datacenter operators for a long time,but remain to be *** resource utilization increases the risk of resource contention between co-located workload,which makes latency-critical(LC)applications suffer unpredictable,and even unacceptable *** of prior work devotes the effort on exploiting effective mechanisms to protect the QoS of LC applications while improving resource *** this paper,we propose MAGI,a resource management runtime that leverages neural networks to monitor and further pinpoint the root cause of performance interference,and adjusts resource shares of corresponding applications to ensure the QoS of LC *** is a practice in Alibaba datacenter to provide on-demand resource adjustment for applications using neural *** experimental results show that MAGI could reduce up to 87.3%performance degradation of LC application when co-located with other antagonist applications.

关键词： resource management neural network resource efficiency tail latency

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Building Agile Workflow Microservice System for HPC Applications Based on Fast-start OSv 27

Building Agile Workflow Microservice System for HPC Applicat...

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27th IEEE International Conference on Parallel and Distributed Systems, ICPADS 2021

作者： Hu, Qiang Ma, Lixian Shao, En Tan, Guangming Institute of Computing Technology CAS State Key Laboratory of Computer Architecture Beijing China University of Chinese Academy of Science Beijing China

ISBN: (纸本)9781665408783

The advances of containers have significantly promoted the development of microservice architecture. This architecture splits a monolithic application into multiple independent components and the container orchestrator manages these components by the container in the cloud environment. The feasibility of deploying high performance computing(HPC) applications as microservices has been proven, but the existing container orchestrator incurs a large performance overhead as there is interference between different containers on the same physical host. In this paper, we design an agile workflow microservice system for HPC applications with fast-start OSv. We consider improving HPC workflow performance from two aspects: single OSv startup time optimization and workflow orchestration optimization. For single OSv startup time optimization, we design a fast-start OSv by analyzing the process of OSv startup and finding an optimization by modifying OSv source code. In this way, we get nearly 50% improvement of startup time. For workflow orchestration optimization, we propose four optimization techniques to speed up the execution of workflow by jointly considering OSv and workflow features, namely: node fusion, node merge, image preload, boot delay. Furthermore, we utilize our fast startup OSv to design an orchestration system for efficiently building an agile HPC workflow microservice by Kubevirt. Our experimental results optimization microservice system reduces the execution time by 30% compared with the original deployment with docker. © 2021 IEEE.

关键词： Containers

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Co-optimization of Dynamic/Static Test PoWer in Scan Test

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电子学报(英文版) 2009年第1期18卷 54-58页

作者： WANG Wei HAN Yinhe LI Xiaowei FANG Fang School of Computer and Information Hefei University of Technology Hefei 230009 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China School of Management Hefei University of Technology Hefei 230009 China

Low-power design has become a challenge of test. We propose an effective low-power scan architecture named PowerSluice to minimize power consumption during scan test, which is based on scan chain modifications. On one hand, a kind of blocking logic is inserted into the scan chain to reduce the dynamic power and two kinds of controlling units are also inserted to decrease the leakage power during the shift cycle. On the other hand, using genetic algorithm, the exact values of control signals are found out to control the process. Experiments results indicate that this architecture can effectually reduce power during scan test with probably minimum area cost.

关键词：低功耗设计扫描测试静态测试动态优化合作控制单元电力消耗动态功耗

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Accelerate Bit Manipulation in XiangShan Processer Using RISC-V B Extension and Instruction Fusion

Accelerate Bit Manipulation in XiangShan Processer Using RIS...

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2022 International Conference on Cloud computing, Internet of Things, and computer Applications, CICA 2022

作者： Zhang, Fawang Tang, Dan Cai, Ye College of Computer Science and Software Engineering Shenzhen University Shenzhen China State Key Laboratory of Computer Architecture Institute of Computing Technology Beijing China

ISBN: (纸本)9781510656673

In the field of high-performance computing, some application scenarios make extensive use of bit manipulation. RISC-V foundation issues B extension to reduce the number of instructions during the static compilation. But this extension does not cover the more frequent operations fully. Instruction fusion technology can fuse multiple instructions into one instruction at the decode stage to dynamically reduce the number of instructions. Therefore, this technology can supplement RISC-V B extension uncovered instruction, enhancing the processor’s capabilities for bit manipulation. This paper implements the RISC-V B extension 1.0 version on the Xiangshan processor. For accelerating more bit manipulation, we profiled general benchmarks by the simulator, proposed ten new instructions fusion targets, and implemented a fusion decode unit. Finally, we use Coremark and SPEC CPU 2006 integer to evaluate the performance. The Coremark results show that dynamic instructions reduce by 18.14%, and the performance improves by 12.09%. © 2022 SPIE.

关键词： Decoding

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