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25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2020

作者： Shui, Chaoyang Yu, Xianzhi Yan, Yujin Wang, Yinshan Meng, Ke Tan, Guangming State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China

ISBN: (纸本)9781450368186

As the widening gap between GPU computing capability and other components (CPU, PCIe bus and communication network), it’s increasingly challenging to design high performance parallel algorithms for large CPU-GPU heterogeneous systems. There are mainly two reasons. Firstly, simply offloading the kernel library to GPU incurs large volume data transfer through low-speed PCIe bus. Secondly, communication overheads through network severely affects scalability. To solve the above issues, we advocate a paradigm shift to GPU-centric and fine-grained pipelining algorithm design. By taking Linpack benchmark as a case study, the new algorithm design paradigm shows its effectiveness. Our optimized Linpack program achieves 63.79PFlops on 16384 GPUs. Its floating-point efficiency outperforms the NVIDIA proprietary counterparts by 5% on average. © 2020 Copyright held by the owner/author(s).

关键词： Graphics processing unit

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On the Cycle Structure of Some Nonlinear Feedback Shift Registers

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Chinese Journal of Electronics 2014年第4期23卷 801-804页

作者： WANG Zhongxiao XU Hong QI Wenfeng State Key Laboratory of Mathematical Engineering and Advanced Computing Zhengzhou Information Science and Technology Institute Department of Computer Science and Engineering Shanghai Jiao Tong University

In this paper, we partly determine the cycle structure of two types of Nonlinear feedback shift registers(NFSRs). Based on these results, the cycle structure of a class of NFSRs with symmetric feedback functions can be completely characterized. Furthermore, an alternative proof of Kjeldsen’s results is presented. Compared with the original proof based on abstract algebra theory, ours is straightforward and easy to understand.

关键词： Cryptography Stream ciphers Nonlinear feedback shift registers Symmetric functions

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HMTT: A hybrid hardware/software tracing system for bridging the DRAM access trace's semantic gap

HMTT: A hybrid hardware/software tracing system for bridging...

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作者： Huang, Yongbing Chen, Licheng Cui, Zehan Ruan, Yuan Bao, Yungang Chen, Mingyu Sun, Ninghui State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China

DRAM access traces (i.e., off-chip memory references) can be extremely valuable for the design of memory subsystems and performance tuning of software. Hardware snooping on the off-chip memory interface is an effective and nonintrusive approach to monitoring and collecting real-life DRAM accesses. However, compared with software-based approaches, hardware snooping approaches typically lack semantic information, such as process/function/object identifiers, virtual addresses, and lock contexts, that is essential to the complete understanding of the systems and software under investigation. In this article, we propose a hybrid hardware/software mechanism that is able to collect off-chip memory reference traces with semantic information. We have designed and implemented a prototype system called HMTT (Hybrid Memory Trace Tool), which uses a custom-made DIMM connector to collect off-chip memory references and a high-level event-encoding scheme to correlate semantic information with memory references. In addition to providing complete, undistorted DRAM access traces, the proposed system is also able to perform various types of low-overhead profiling, such as object-relative accesses and multithread lock accesses. © 2014 ACM.

关键词： Dynamic random access storage

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Fault diagnosis of arbiter physical unclonable function 20

Fault diagnosis of arbiter physical unclonable function

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20th Design, Automation and Test in Europe, DATE 2017

作者： Ye, Jing Quo, Qingli Hu, Yu Li, Xiaowei State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China

ISBN: (纸本)9783981537093

Physical Unclonable Function (PUF) has broad application prospects in the field of hardware security. If faults happen in PUF during manufacturing, the security of whole chip will be threatened. Fault diagnosis plays an important role in the yield learning process. However, since different manufactured PUFs with the same design have different Challenge-Response Pairs (CRPs), which cannot be predicted, the traditional fault diagnosis method based on comparing the fault-free responses of a design and the failing responses of chips is no longer suitable for diagnosing PUF. Therefore, this paper proposes a fault diagnosis method toward classic arbiter PUF. The stuck-at faults and the delay faults are considered. Based on the expected uniformity of arbiter PUF, a diagnostic challenge generation method and a corresponding CRP analysis method are proposed to distinguish faults within the arbiter PUF. Experimental results show that the diagnostic accuracy achieves 100.0% with good diagnostic resolution. © 2017 IEEE.

关键词： Failure analysis

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OeIM: An optoelectronic interconnection middleware for the exascale computer 21

OeIM: An optoelectronic interconnection middleware for the e...

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21st IEEE International Conference on High Performance computing and Communications, 17th IEEE International Conference on Smart City and 5th IEEE International Conference on Data Science and Systems, HPCC/SmartCity/DSS 2019

作者： Shao, En Tan, Guangming Wang, Zhan Sun, Ninghui State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781728120584

During the improved process of hardware technology and program optimization in the high-performance computer (HPC), the overall computing ability of supercomputer increases correspondingly. As a large-scale system and a milestone to the HPC community shortly, the envisioned exascale computer will be comprised of nearly 5000 interconnected nodes and tens of thousands of computing nodes. Interconnection innovations in such a system are critical to improving overall computing ability. In this paper, we investigate optoelectronic interconnection in an exascale computer system design. Here, we propose a new software stack called Optoelectronic Interconnection Middleware (OeIM) to enable efficient utilization of the optical interconnection. OeIM allows for the use of two novel functions, namely the reconfigurable function and the running-time function. We evaluate OeIM using both communication benchmark (IMB) and real-world motif applications (Linpack, HPCG, and Graph500) in a prototyped exascale computer. The experiment shows that OeIM reduced latency by form 20 to 35% in the large-range communication, improved throughput by 30% in the long-distance communication, and improved the motif applications by more than 10%. Together, our results demonstrate that OeIM is an effective bridge between the optical switching device and system scheduler to improve communication capability. © 2019 IEEE.

关键词： Middleware

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Deep Reinforcement Agent for Failure-aware Job scheduling in High-Performance computing 27

Deep Reinforcement Agent for Failure-aware Job scheduling in...

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27th IEEE International Conference on Parallel and Distributed Systems, ICPADS 2021

作者： Yang, Kang Cao, Rongyu Zhou, Yueyuan Zhang, Jiawei Shao, En Tan, Guangming Institute of Computing Technology CAS State Key Laboratory of Computer Architecture Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665408783

Job scheduling is crucial in high-performance computing (HPC), which is dedicated to deciding when and which jobs are allocated to the system and placing the jobs on which resources, by considering multiple scheduling goals. Along with the incremental of various resources and dazzling deep learning training (DLT) workloads, job failure becomes a quite common issue in HPC, which will affect user satisfaction and cluster utilization. To alleviate the influence of hardware and software errors as much as possible, in this paper, we aim to tackle the problem of failure-aware job scheduling in HPC clusters. Inspired by the success of previous studies of deep reinforcement learning-driven job scheduling, we propose a novel HPC scheduling agent named FARS (Failure-aware RL-based scheduler) by considering the effects of job failures. On the one hand, a neural network is applied to map the information of raw cluster and job states to job placement decisions. On the other hand, to consider the influence of job failure for user satisfaction and cluster utilization, FARS leverages make-span of the entire workload as the training objective. Additionally, effective exploration and experience replay techniques are applied to obtain effectively converged agent. To evaluate the capability of FARS, we design extensive trace-based simulation experiments with the popular DLT workloads. The experimental results show that, compared with the best baseline model, FARS obtains 5.69% improvement of average make-span under different device error rates. Together, our FARS is an ideal candidate for failure-aware job scheduler in HPC clusters. © 2021 IEEE.

关键词： Scheduling

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Virtual resource monitoring in cloud computing

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Journal of Shanghai University(English Edition) 2011年第5期15卷 381-385页

作者：韩芳芳彭俊杰张武李青李建敦江钦龙袁勤 School of Computer Engineering and Science Shanghai University Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Science

Cloud computing is a new computing model. The resource monitoring tools are immature compared to traditional distributed computing and grid computing. In order to better monitor the virtual resource in cloud computing, a periodically and event-driven push （PEP） monitoring model is proposed. Taking advantage of the push and event-driven mechanism, the model can provide comparatively adequate information about usage and status of the resources. It can simplify the communication between Master and Work Nodes without missing the important issues happened during the push interval. Besides, we develop ＂mon＂ to make up for the deficiency of Libvirt in monitoring of virtual CPU and memory.

关键词： virtual resource monitoring cloud computing virtualization

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Energy-Efficient and Reliable Federated Learning in Heterogeneous Mobile-Edge computing 19

Energy-Efficient and Reliable Federated Learning in Heteroge...

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2022 IEEE SmartWorld, 19th IEEE International Conference on Ubiquitous Intelligence and computing, 2022 IEEE International Conference on Autonomous and Trusted Vehicles Conference, 22nd IEEE International Conference on Scalable computing and Communications, 2022 IEEE International Conference on Digital Twin, 8th IEEE International Conference on Privacy computing and 2022 IEEE International Conference on Metaverse, SmartWorld/UIC/ATC/ScalCom/DigitalTwin/PriComp/Metaverse 2022

作者： Xu, Yan Li, Liying Cong, Peijin Zhou, Junlong Nanjing University of Science and Technology School of Computer Science and Engineering China Institute of Computing Technology Chinese Academy of Sciences State Key Laboratory of Computer Architecture China

ISBN: (纸本)9798350346558

As a decentralized machine learning paradigm, Federated Learning (FL) is an emerging technique to protect user data privacy in Mobile Edge computing (MEC). FL adopts the idea of distributed privacy computing, enabling the terminal devices to train machine learning models required by servers locally and upload model parameters to servers for aggregation. However, in the process of coupling FL with MEC systems, device heterogeneity, malicious use of poisoned data by users and limited system resources will seriously affect FL training accuracy, system reliability and energy efficiency. In this paper, a highly reliable and energy-efficient FL scheme is designed to solve these issues. Specifically, we first propose a calculation method for estimating the reliability of heterogeneous devices. Then, we design a highly reliable device selection scheme based on devices' reliability, computing power, and participation times. Finally, we utilize the slack time in FL training to dynamically adjust the voltage and frequency of devices for reducing the energy consumption of training. Experimental results show that our proposed scheme improves the accuracy by up to 36.45% on average and saves energy by up to 48.63% when compared to the baseline and benchmarking methods. © 2022 IEEE.

关键词： Reliability

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Software Defect Prediction via Deep Belief Network

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Chinese Journal of Electronics 2019年第5期28卷 925-932页

作者： WEI Hua SHAN Chun HU Changzhen ZHANG Yu YU Xiao School of Computer Science and Technology Beijing Institute of Technology China Information Technology Security Evaluation Center Beijing Key Laboratory of Software Security Engineering Technology Beijing Institute of Technology School of Electrical and Information Engineering and Beijing Key Laboratory of Intelligent Processing for Building Big Data Beijing University of Civil Engineering and Architecture State Key Laboratory in China for Geomechanics and Deep Underground Engineering (Beijing) China University of Mining and Technology School of Computer Science and Technology Shandong University of Technology

Defect distribution prediction is a meaningful topic because software defects are the fundamental cause of many attacks and data loss. Building accurate prediction models can help developers find bugs and prioritize their testing efforts. Previous researches focus on exploring different machine learning algorithms based on the features that encode the characteristics of *** problem of data redundancy exists in software defect data set, which has great influence on prediction *** propose a defect distribution prediction model(Deep belief network prediction model, DBNPM), a system for detecting whether a program module contains defects. The key insight of DBNPM is Deep belief network(DBN)technology, which is an effective deep learning technique in image processing and natural language processing,whose features are similar to defects in source *** results show that DBNPM can efficiently extract and process the data characteristics of source program and the performance is better than Support vector machine(SVM), Locally linear embedding SVM(LLE-SVM), and Neighborhood preserving embedding SVM(NPE-SVM).

关键词： Defect prediction Software security Deep belief network(DBN)

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A Robust and Power-Effcient SoC Implementation in 65nm

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Journal of computer Science & technology 2013年第4期28卷 682-688页

作者：肖斌张译夫高燕萍杨梁吴冬梅范宝峡 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences Loongson Technology Corporation Limited

Godson2H is a complex SoC （System-on-Chip） of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65 nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design.

关键词： System-on-Chip on-chip-variation PVT detector low power hierarchical design flow

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