检索结果-内蒙古大学图书馆

作者： Fan, Dong-Rui Li, Xiao-Wei Li, Guo-Jie Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Moore's law continues to grant computer architects ever more transistors in the foreseeable future, and para-llelism is the key to continued performance scaling in modern microprocessors. In this paper, the achievements in our research project, which is supported by the National Basic Research 973 Program of China, on parallel architecture, are systematically presented. The innovative approaches and techniques to solve the significant problems in parallel architecture design are summarized, including architecture level optimization, compiler and language-supported technologies, reliability, power-performance efficient design, test and verification challenges, and platform building. Two prototype chips, a multi-heavy-core Godson-3 and a many-light-core Godson-T, are described to demonstrate the highly scalable and reconfigurable parallel architecture designs. We also present some of our achievements appearing in ISCA, MICRO, ISSCC, HPCA, PLDI, PACT, IJCAI, Hot Chips, DATE, IEEE Trans. VLSI, IEEE Micro, IEEE Trans. computers, etc. © 2011 Springer Science+Business Media, LLC & Science Press, China.

关键词： Parallel architectures

来源：评论

学校读者我要写书评

暂无评论

TSCMR:Two-Stage Cross-Modal Retrieval 9th

TSCMR:Two-Stage Cross-Modal Retrieval

引用

19th International Conference on Advanced Data Mining and Applications, ADMA 2023

作者： Chen, Zhihao Wang, Hongya School of Computer Science and Technology Donghua University Shanghai China State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China Shanghai Key Laboratory of Computer Software Evaluating and Testing Shanghai China

ISBN: (纸本)9783031466731

Currently, large-scale vision and language models has significantly improved the performances of cross-modal retrieval tasks. However, large-scale models require a substantial amount of computing resources, so the execution of these models on devices with limited resources is challenging. Thus, it is paramount to reduce the model size and minimize computing costs of a model without sacrificing its performance. In this paper, we improved TERAN by dividing cross-modal retrieval into two stages: image-text coarse-grained matching and image-text fine-grained matching. Specifically, we present a novel approach called Two-Stage Cross-Modal Retrieval network(TSCMR). To reduce model size after model training, our approach utilized a new knowledge distillation method for Transformer-based models. Experiments have shown that our approach maintains a performance comparable to TERAN on the MS-COCO 1K test set, while being 2x smaller and 3.1x faster on inference. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Distillation

来源：评论

学校读者我要写书评

暂无评论

Fast implementation of DGEMM on Fermi GPU

Fast implementation of DGEMM on Fermi GPU

引用

2011 International Conference for High Performance computing, Networking, Storage and Analysis, SC11

作者： Tan, Guangming Li, Linchuan Triechle, Sean Phillips, Everett Bao, Yungang Sun, Ninghui Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Science China Nvidia Corporation China

ISBN: (纸本)9781450307710

In this paper we present a thorough experience on tuning double-precision matrix-matrix multiplication (DGEMM) on the Fermi GPU architecture. We choose an optimal algorithm with blocking in both shared memory and registers to satisfy the constraints of the Fermi memory hierarchy. Our optimization strategy is further guided by a performance modeling based on micro-architecture benchmarks. Our optimizations include software pipelining, use of vector memory operations, and instruction scheduling. Our best CUDA algorithm achieves comparable performance with the latest CUBLAS library1. We further improve upon this with an implementation in the native machine language, leading to 20% increase in performance. That is, the achieved peak performance (efficiency) is improved from 302Gflop/s (58%) to 362Gflop/s (70%). Copyright 2011 ACM.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

The design methodology of phoenix cluster system software stack

The design methodology of phoenix cluster system software st...

引用

2007 Asian technology Information Program's (ATIP's) 3rd Workshop on High Performance computing in China - Solution Approaches to Impediments for High Performance computing, CHINA HPC'07

作者： Zhan, Jianfeng Wang, Lei Tu, Bibo Wang, Hui Zhang, Zhihong Jin, Yi Wen, Yu Chen, Yuansheng Wang, Peng Qiu, Bizhu Meng, Dan Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China

ISBN: (纸本)9781595939036

Though many research groups have explored the design methodology of cluster system software stack, few works discuss what constitutes a good one. In this paper, we choose four criteria throughout the lifecycle of cluster system software stack to evaluate its design methodology, including code reusability, evolveability, adaptability and manageability. According to the four criteria, we have proposed a management service-based layered design methodology and built a complete cluster system software stack for both scientific and business computing. Our practices and evaluations show our design methodology has advantages over others in terms of the proposed criteria. Copyright 2007 ACM.

关键词： Reusability

来源：评论

学校读者我要写书评

暂无评论

A Hybrid Circular Queue Method for Iterative Stencil Computations on GPUs

引用

Journal of computer Science & technology 2012年第1期27卷 57-74页

作者： Yang Yang Hui-Min Cui Xiao-Bing Feng Jing-Ling Xue State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China Programming Languages and Compilers Group School of Computer Science and Engineering University of New South WalesSydneyNSW 2052Australia

In this paper, we present a hybrid circular queue method that can significantly boost the performance of stencil computations on GPU by carefully balancing usage of registers and shared-memory. Unlike earlier methods that rely on circular queues predominantly implemented using indirectly addressable shared memory, our hybrid method exploits a new reuse pattern spanning across the multiple time steps in stencil computations so that circular queues can be implemented by both shared memory and registers effectively in a balanced manner. We describe a framework that automatically finds the best placement of data in registers and shared memory in order to maximize the performance of stencil computations. Validation using four different types of stencils on three different GPU platforms shows that our hybrid method achieves speedups up to 2.93X over methods that use circular queues implemented with shared-memory only.

关键词： stencil computation circular queue GPU occupancy register

来源：评论

学校读者我要写书评

暂无评论

An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits

引用

Frontiers of computer Science 2017年第4期11卷 728-742页

作者： Zhenxue HE Limin XIAO Fei GU Tongsheng XIA Shubin SU Zhisheng HUO Rong ZHANG Longbing ZHANG Li RUAN Xiang WANG State Key Laboratory of Software Development Environment Beihang University Beijing 100191 China School of Computer Science and Engineering Beihang University Beijing 100191 China School of Electronic and Information Engineering Beihang University Beijing 100191 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China National Engineering Research Center for Science & Technology Resources Sharing Service Beijing 100191 China

Although the genetic algorithm has been widely used in the polarity optimization of mixed polarity Reed- Muller （MPRM） logic circuits, few studies have taken into account the polarity conversion sequence. In order to im- prove the efficiency of polarity optimization of MPRM logic circuits, we propose an efficient and fast polarity optimiza- tion approach （FPOA） considering the polarity conversion se- quence. The main idea behind the FPOA is that, firstly, the best polarity conversion sequence of the polarity set wait- ing for evaluation is obtained by using the proposed hybrid genetic algorithm （HGA）; secondly, each of polarity in the polarity set is converted according to the best polarity con- version sequence obtained by HGA. Our proposed FPOA is implemented in C and a comparative analysis has been pre- sented for MCNC benchmark circuits. The experimental re- suits show that for the circuits with more variables, the FPOA is highly effective in improving the efficiency of polarity op- timization of MPRM logic circuits compared with the tradi- tional polarity optimization approach which neglects the po- larity conversion sequence and the improved polarity opti- mization approach with heuristic technique.

关键词： genetic algorithm polarity optimization mixed

来源：评论

学校读者我要写书评

暂无评论

Design automation methodology from RTL to gate-level netlist and schematic for RSFQ logic circuits 20

Design automation methodology from RTL to gate-level netlist...

引用

30th Great Lakes Symposium on VLSI, GLSVLSI 2020

作者： Fu, Rongliang Zhang, Zhi-Min Tang, Guang-Ming Huang, Junying Ye, Xiao-Chun Fan, Dong-Rui Sun, Ning-Hui State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China School of Computer Science and Technology University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450379441

The superconducting rapid single flux quantum (RSFQ) logic circuit has the characteristics of high speed and low power consumption, making it an attractive candidate for future supercomputers. However, computer-aided design (CAD) tools for CMOS cannot be directly applied to RSFQ logic due to their distinct properties. For instance, the RSFQ logic gate can work properly when all its fan-ins have the same logic level. This paper presents the design flow from RTL to RSFQ logic netlist and schematic. First, we implement logic synthesis for RSFQ logic circuits. It achieves path balancing while minimizing the number of DFFs. In addition, we propose an automatic schematic generator for the RSFQ logic circuits. It converts the synthesized netlist into its equivalent schematic. A layer assignment algorithm is proposed, which makes all gates layered in the order of the clock arrival time. Experimental results with ISCAS85 and EPFL benchmarks along with some Kogge-Stone adders have shown a 29.2% reduction in the number of DFFs over the breadth-first first search;moreover, 59.57% and 5.3% decrease in the number of layers of the schematic and number of edge crossings over the ELK tool. © 2020 Association for computing Machinery.

关键词： Logic circuits

来源：评论

学校读者我要写书评

暂无评论

H-DB: Yet another big data hybrid system of Hadoop and DBMS

H-DB: Yet another big data hybrid system of Hadoop and DBMS

引用

13th International Conference on Algorithms and architectures for Parallel Processing, ICA3PP 2013

作者： Luo, Tao Chen, Guoliang Zhang, Yunquan School of Computer Science and Technology University of Science and Technology of China 230027 Hefei China State Key Laboratory of Computer Architecture Institute of Computing Technology CAS 100190 Beijing China

ISBN: (纸本)9783319038582

With the explosion of the amount of data, analytics applications require much higher performance and scalability. However, traditional DBMS encounters the tough obstacle of scalability, and could not handle big data easily. In the meantime, due to the complex relational data model, the large amount of historical data and the independent demand of subsystems, it is not suitable to use either shared-nothing MPP architecture (e.g. Hadoop) or existing hybrid architecture (e.g. HadoopDB) to replace completely. In this paper, considering the feasibility and versatility of building a hybrid system, we propose a novel prototype H-DB which takes DBMSs as the underlying storage and execution units, and Hadoop as an index layer and a cache. H-DB not only retains the analytical DBMS, but also could handle the demands of rapidly exploding data applications. The experiments show that H-DB meets the demand, outperforms original system and would be appropriate for analogous big data applications. © Springer International Publishing Switzerland 2013.

关键词： Database systems

来源：评论

学校读者我要写书评

暂无评论

A lightweight hybrid hardware/software approach for object-relative memory profiling

A lightweight hybrid hardware/software approach for object-r...

引用

2012 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2012

作者： Chen, Licheng Cui, Zehan Bao, Yungang Chen, Mingyu Huang, Y. Tan, Guangming State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate School of Chinese Academy of Sciences China

ISBN: (纸本)9781467311441

Memory profiling is the process of collecting memory address traces during the execution of a program, then analyzing and characterizing the memory behavior of the program offline. With the trend that there will be more and more cores integrated in a processor chip, the Memory Wall problem will become more serious in the chip multiprocessor (CMP) system. Thus accurate and effective memory profiling is becoming one of the keys to identify the source of memory system bottlenecks. A large body of work has been contributed to memory profiling, however, most adopts instrumentation, simulator which suffers heavy overhead, or hardware performance counter which is lack of detail trace information. Furthermore, correlating the raw memory address traces with object-relative information allows us to separate regular pattern for certain object from the irregular mixed, thus helps the optimization. In this paper, we propose a lightweight hybrid hardware/software approach for object-relative memory profiling. We monitor physical memory addresses through hardware snooping with negligible overhead;meanwhile we dump Linux kernel page tables of processes, as well as object-relative memory allocation information. Our approach supports not only to collect applications' full memory traces with detail object relative information, but also to identify hardware-generated memory accesses such as page memory walks due to TLB miss at object level. The experimental results on real system show that our approach is highly accurate (the largest error is 2.04%) and low overhead (the average overhead is 1.60%). Furthermore, we profile two multi-thread applications in detail, and successfully identity hot TLB-miss objects. With object-targeted optimization, we can improve applications' performance by nearly 6.86%. © 2012 IEEE.

关键词： computer operating systems

来源：评论

学校读者我要写书评

暂无评论

LINEAR SYMMETRIC QUANTIZATION OF NEURAL NETWORKS FOR LOW-PRECISION INTEGER HARDWARE 8

LINEAR SYMMETRIC QUANTIZATION OF NEURAL NETWORKS FOR LOW-PRE...

引用

8th International Conference on Learning Representations, ICLR 2020

作者： Zhao, Xiandong Wang, Ying Cai, Xuyi Liu, Cheng Zhang, Lei Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China State Key Laboratory of Computer Architecture China

With the proliferation of specialized neural network processors that operate on low-precision integers, the performance of Deep Neural Network inference becomes increasingly dependent on the result of quantization. Despite plenty of prior work on the quantization of weights or activations for neural networks, there is still a wide gap between the software quantizers and the low-precision accelerator implementation, which degrades either the efficiency of networks or that of the hardware for the lack of software and hardware coordination at design-phase. In this paper, we propose a learned linear symmetric quantizer for integer neural network processors, which not only quantizes neural parameters and activations to low-bit integer but also accelerates hardware inference by using batch normalization fusion and low-precision accumulators (e.g., 16-bit) and multipliers (e.g., 4-bit). We use a unified way to quantize weights and activations, and the results outperform many previous approaches for various networks such as AlexNet, ResNet, and lightweight models like MobileNet while keeping friendly to the accelerator architecture. Additional, we also apply the method to object detection models and witness high performance and accuracy in YOLO-v2. Finally, we deploy the quantized models on our specialized integer-arithmetic-only DNN accelerator to show the effectiveness of the proposed quantizer. We show that even with linear symmetric quantization, the results can be better than asymmetric or non-linear methods in 4-bit networks. In evaluation, the proposed quantizer induces less than 0.4% accuracy drop in ResNet18, ResNet34, and AlexNet when quantizing the whole network as required by the integer processors. © 2020 8th International Conference on Learning Representations, ICLR 2020. All rights reserved.

关键词： Chemical activation

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：