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Deterministic Circular Self Test Path

Tsinghua Science and technology 2007年第S1期12卷 20-25页

作者：文科胡瑜李晓维 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences

Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental re- sults on ISCAS’89 benchmarks show that 100% fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.

关键词： very large scale integration (VLSI) test built-in-self-test (BIST) circular self test path deterministic

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UAV-Aided Covert Federated Learning Networks

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IEEE Network 2025年

作者： Wang, Chao Guo, Shaoyong Xiong, Zehui Xing, Chengwen Zhao, Nan Niyato, Dusit Karagiannidis, George Dalian University of Technology School of Information and Communication Engineering Dalian116024 China Beijing University of Posts and Telecommunications State Key Laboratory of Networking and Switching Technology Beijing100876 China Singapore University of Technology and Design Information Systems Technology and Design Pillar 487372 Singapore Beijing Institute of Technology School of Information and Electronics Beijing100081 China Nanyang Technological University College of Computing and Data Science 639798 Singapore Aristotle University of Thessaloniki Department of Electrical and Computer Engineering Greece

With the increasing emphasis on data privacy, federated learning (FL) networks show great potential through distributed training without directly sharing the raw data. However, the coverage of FL terrestrial servers is usually limited. Therefore, we propose leveraging the unmanned aerial vehicle (UAV) as a mobile flying server to further improve the wireless coverage and training efficiency of FL. Nevertheless, frequent exchanges of model parameters in UAV-assisted FL can result in serious security risks. In order to achieve this, we propose a covert FL scheme assisted by the UAV, which can protect the transmission key features of local models from being detected by wardens. Furthermore, we discuss the FL network and covert communications, as well as the exceptional features of UAV-assisted covert FL. Finally, we present two case studies, one of which focuses on minimising the network latency, while the other concentrates on reducing the energy consumption of covert FL. The simulation results demonstrate the efficacy of the proposed schemes in addressing future challenges. © 1986-2012 IEEE.

关键词： Data privacy

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A dynamic platform for global pullorum disease and fowl typhoid

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Animal Diseases 2025年第1期5卷 113-123页

作者： Xiamei Kang Canghong Jin Pengkun Gu Song Wang Zhengjie Gao Chenyi Dai Xiao Zhou Abubakar Siddique Haiyang Zhou Linlin Huang Yan Li Min Yue Department of Veterinary Medicine Zhejiang University College of Animal SciencesHangzhou 310058China School of Computer and Computing Science Hangzhou City UniversityHangzhou 310015China Hainan Institute of Zhejiang University Sanya 572000China School of Life Science Hangzhou Institute for Advanced StudyUniversity of Chinese Academy of SciencesHangzhou 310024China State Key Laboratory for Diagnosis and Treatment of Infectious Diseases National Clinical Research Center for Infectious DiseasesNational Medical Center for Infectious DiseasesThe First Affiliated HospitalCollege of MedicineZhejiang UniversityHangzhou 310003China Ningbo Academy of Agricultural Sciences Ningbo 315040China NewFit(Hangzhou)Information Technology Co. LtdHangzhou 310000China

Pullorum disease and fowl typhoid are caused by the Salmonella serovars Gallinarum biovars Pullorum and Gal-linarum,*** prevalence of these diseases varies across regions and is affected by different risk fac-tors that remain insufficiently *** fill this knowledge gap,we have compiled a global dataset for its prevalence,drawing upon a collection of literature from the last seven decades obtained from bilingual ***,a more interactive and dynamic platform is still needed for both academics and policymakers to improve biosecurity measures,limit disease transmission,and prevent future outbreaks at the global and local ***,we developed an advanced visualization platform to depict the prevalence of Salmonella Pullorum and Gallinarum,espe-cially in China,which is categorized by geographical region and temporal *** platform offers a user-friendly,efficient,and visually engaging tool to explore the prevalence of pullorum disease and fowl typhoid between 1945 and 2021 in different ***,this platform allows users to understand the influence of various fac-tors,such as breed,farm mode,economic usage and even the sex of the primary host,chickens,on the prevalence of this *** further provided a detailed overview of individual province within *** particular,by selecting two different provinces on the interface,users can quickly visualize and grasp the disparities in disease prevalence between the chosen *** interactive toolkit enables a dynamic exploration of the patterns and factors con-tributing to the prevalence of Salmonella Pullorum and *** interactive platform is freely available open source at http://139.9.85.208/.

关键词： Pullorum disease Fowl typhoid Interactive platform Prevalence prediction

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A survey of neural network accelerators

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Frontiers of computer Science 2017年第5期11卷 746-761页

作者： Zhen LI Yuqing WANG Tian ZHI Tianshi CHEN State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer Science and Technology University of Science and Technology of China Hefei 230026 China

Machine-learning techniques have recently been proved to be successful in various domains, especially in emerging commercial applications. As a set of machine- learning techniques, artificial neural networks （ANNs）, requiring considerable amount of computation and memory, are one of the most popular algorithms and have been applied in a broad range of applications such as speech recognition, face identification, natural language processing, ect. Conventionally, as a straightforward way, conventional CPUs and GPUs are energy-inefficient due to their excessive effort for flexibility. According to the aforementioned situation, in recent years, many researchers have proposed a number of neural network accelerators to achieve high performance and low power consumption. Thus, the main purpose of this literature is to briefly review recent related works, as well as the DianNao-family accelerators. In summary, this review can serve as a reference for hardware researchers in the area of neural networks.

关键词： neural networks accelerators FPGAs ASICs,DianNao series

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Green challenges to system software in data centers

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中国计算机科学前沿 2011年第3期5卷 353-368页

作者： Yuzhong SUN Yiqiang ZHAO Ying SONG Yajun YANG Haifeng FANG Hongyong ZANG Yaqiong LI Yunwei GAO Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100190 China

With the increasing demand and the wide application of high performance commodity multi-core processors,both the quantity and scale of data centers grow dramatically and they bring heavy energy *** and engineers have applied much effort to reducing hardware energy consumption,but software is the true consumer of power and another key in making better use of *** software is critical to better energy utilization,because it is not only the manager of hardware but also the bridge and platform between applications and *** this paper,we summarize some trends that can affect the efficiency of data ***,we investigate the causes of software *** on these studies,major technical challenges and corresponding possible solutions to attain green system software in programmability,scalability,efficiency and software architecture are ***,some of our research progress on trusted energy efficient system software is briefly introduced.

关键词： green software multi-core data center power efficient system software

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SCIENTISTS RECONSIDER LOW-ENERGY NUCLEAR REACTIONS It's absolutely, definitely, seriously not cold fusion

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IEEE SPECTRUM 2018年第12期55卷 10-11页

作者： Koziol, Michael State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences

It's been a big year for low-energy nuclear reactions. LENRs, as they're known, are a fringe research topic that some physicists think could explain the results of an infamous experiment nearly 30 years ago that formed the basis for the idea of cold fusion. That idea didn't hold up, and only a handful of researchers around the world have continued trying to understand the mysterious nature of the inconsistent, heat-generating reactions that had spurred those claims.

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Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

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Journal of computer Science & technology 2008年第6期23卷 1037-1046页

作者：王达胡瑜李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences

This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test （BIST） circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops （PLL） to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation （ATPG） and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing （HVM） DFT plan to meet high quality test goals as well as slow test power consumption and cost.

关键词： microprocessor design-for-testability test generation built-in self-test at-speed testing

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Selected Crosstalk Avoidance Code for Reliable Network-on-Chip

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Journal of computer Science & technology 2009年第6期24卷 1074-1085页

作者：张颖李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Graduate School of the Chinese Academy of Sciences

With the shrink of the technology into nanometer scale, network-on-chip （NOC） has become a reasonable solution for connecting plenty of IP blocks on a single chip. But it suffers from both crosstalk effects and single event upset （SEU）, especially crosstalk-induced delay, which may constrain the overall performance of NOC. In this paper, we introduce a reliable NOC design using a code with the capability of both crosstalk avoidance and single error correction. Such a code, named selected crosstalk avoidance code （SCAC） in our previous work, joins crosstalk avoidance code （CAC） and error correction code （ECC） together through codeword selection from an original CAC codeword set. It can handle possible error caused by either crosstalk effects or SEU. When designing a reliable NOC, data are encoded to SCAC codewords and can be transmitted rapidly and reliably across NOC. Experimental results show that the NOC design with SCAC achieves higher performance and is reliable to tolerate single errors. Compared with previous crosstalk avoidance methods, SCAC reduces wire overhead, power dissipation and the total delay. When SCAC is used in NOC, it can save 20% area overhead and reduce 49% power dissipation.

关键词： crosstalk avoidance codeword selection reliable network-on-chip single event upset

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Landing Stencil Code on Godson-T

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Journal of computer Science & technology 2010年第4期25卷 886-894页

作者：崔慧敏王蕾范东睿冯晓兵 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences

The advent of multi-core/many-core chip technology offers both an extraordinary opportunity and a profound challenge. In particular, computer architects and system software designers are faced with a unique opportunity to introducing new architecture features as well as adequate compiler technology -- together they may have profound impact. This paper presents a case study （using the 1-D Jacobi computation） of compiler-amendable performance optimization techniques on a many-core architecture Godson-T. Godson-T architecture has several unique features that are chosen for this study： 1） chip-level global addressable memory in particular the scratchpad memories （SPM） local to the processing cores; 2） fine-grain memory based synchronization （e.g., full-empty bit for fine-grain synchronization）. Leveraging state-of-the-art performance optimization methods for 1-D stencil parallelization （e.g., timed tiling and variants）, we developed and implement a number of many-core-based optimization for Godson-T. Our experimental study shows good performance in both execution time speedup and scalability, validate the value of globally accessed SPM and fine-grain synchronization mechanism （full-empty bits） under the Godson-T, and provides some useful guidelines for future compiler technology of many-core chip architectures.

关键词： many-core, stencil, Jacobi, compiler SPM, fine-grain synchronization

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Automatic tuning of sparse matrix-vector multiplication on multicore clusters

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Science China(Information Sciences) 2015年第9期58卷 17-30页

作者： LI ShiGang HU ChangJun ZHANG JunChao ZHANG YunQuan State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences School of Computer and Communication Engineering University of Science and Technology Beijing Department of Computer Science University of Illinois at Urbana-Champaign

To have good performance and scalability, parallel applications should be sophisticatedly optimized to exploit intra-node parallelism and reduce inter-node communication on multicore clusters. This paper investigates the automatic tuning of the sparse matrix-vector(Sp MV) multiplication kernel implemented in a partitioned global address space language, which supports a hybrid thread- and process-based communication layer for multicore systems. One-sided communication is used for inter-node data exchange, while intra-node communication uses a mix of process shared memory and multithreading. We develop performance models to facilitate selecting the best configuration of threads and processes hybridization as well as the best communication pattern for Sp MV. As a result, our tuned Sp MV in the hybrid runtime environment consumes less memory and reduces inter-node communication volume, without damaging the data locality. Experiments are conducted on 12 real sparse matrices. On 16-node Xeon and 8-node Opteron clusters, our tuned Sp MV kernel gets on average 1.4X and 1.5X improvement in performance over the well-optimized process-based message-passing implementation, respectively.

关键词： Sp MV PGAS hybridization model-driven multicore clusters

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