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High Performance General-Purpose Microprocessors： Past and Future

Journal of computer Science & technology 2006年第5期21卷 631-640页

作者：胡伟武侯锐肖俊华章隆宾 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 P.R. China

It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to simple, and new innovative architecture will emerge to utilize the continuously increasing transistor budgets. The growing importance of wire delays, changing workloads, power consumption, and design/verification complexity will drive the forthcoming era of Chip Multiprocessors （CMPs）. Furthermore, typical CMP projects both from industries and from academics are investigated. Through going into depths for some primary theoretical and implementation problems of CMPs, the great challenges and opportunities to future CMPs are presented and discussed. Finally, the Godson series microprocessors designed in China are introduced.

关键词： high performance general-purpose microprocessor instruction level parallelism data level parallelism thread level parallelism chip multiprocessors Godson processor

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DimRouter： A Multi-Mode Router architecture for Higher Energy-Proportionality of On-Chip Networks

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Journal of computer Science & technology 2018年第5期33卷 984-997页

作者： Shi-Qi Lian Ying Wang Yin-He Han State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China

In the dark silicon era, many independent components of many-core processors are becoming voluntarily inactive due to the constraint of power consumption on a chip. However, to keep network connectivity, the on-chip interconnection must still be kept activated and wastes considerable energy to avoid the isolation of these inactive components, harming the energy-proportionality of the whole processor chip. In this paper, we propose a novel design to provide more energy- proportional on-chip connection without damaging the network connectivity. To achieve this goal, we redesign the router architecture. The new architecture, DimRouter, supports three modes： normal, dark and dim. In the dim mode, only part of the router is active and provides flexible connection while the dark mode puts all router elements in the asleep state. Moreover, to maximize the number of dark routers, we also propose a reconfiguration algorithm based on degree-constrained Steiner Tree. The evaluation result under synthetic traffic shows that the new design can reduce the energy consumption up to 85% compared with the common design. For real application traffic, the new design can also save average 46% energy consumption with 4% performance improvement.

关键词： dark silicon energy-proportion power gating topology reconfiguration

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TransGPerf:Exploiting Transfer Learning for Modeling Distributed Graph Computation Performance

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Journal of computer Science & technology 2021年第4期36卷 778-791页

作者： Songjie Niu Shimin Chen State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China

It is challenging to model the performance of distributed graph *** formulation cannot easily capture the diversified factors and complex interactions in the *** learning methods require a large number of training samples to generate an accurate prediction ***,it is time-consuming to run the required graph computation tests to obtain the training *** this paper,we propose TransGPerf,a transfer learning based solution that can exploit prior knowledge from a source scenario and utilize a manageable amount of training data for modeling the performance of a target graph computation *** results show that our proposed method is capable of generating accurate models for a wide range of graph computation tasks on PowerGraph and *** outperforms transfer learning methods proposed for other applications in the literature.

关键词： performance modeling distributed graph computation deep learning transfer learning

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Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage computing

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Journal of computer Science & technology 2016年第2期31卷 253-266页

作者： Xin He Gui-Hai Yan Yin-He Han Xiao-Wei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China

The load power range of modern processors is greatly enlarged because many advanced power management techniques are employed, such as dynamic voltage frequency scaling, Turbo Boosting, and near-threshold voltage （NTV） technologies. However, because the efficiency of power delivery varies greatly with different load conditions, conventional power delivery designs cannot maintain high efficiency over the entire voltage spectrum, and the gained power saving may be offset by power loss in power delivery. We propose SuperRange, a wide operational range power delivery unit. SuperRange complements the power delivery capability of on-chip voltage regulator and off-chip voltage regulator. On top of SuperRange, we analyze its power conversion characteristics and propose a voltage regulator （VR） aware power management algorithm. Moreover, as more and more cores have been integrated on a singe chip, multiple SuperRange units can serve as basic building blocks to build, in a highly scalable way, more powerful power delivery subsystem with larger power capacity. Experimental results show SuperRange unit offers lx and 1.3x higher power conversion efficiency （PCE） than other two conventional power delivery schemes at NTV region and exhibits an average 70% PCE over entire operational range. It also exhibits superior resilience to power-constrained systems.

关键词： voltage regulator power delivery near-threshold computing multicore processor

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A Survey of Phase Change Memory Systems

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Journal of computer Science & technology 2015年第1期30卷 121-144页

作者：夏飞蒋德钧熊劲孙凝晖 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China

As the scaling of applications increases, the demand of main memory capacity increases in order to serve large working set. It is difficult for DRAM （dynamic random access memory） based memory system to satisfy the memory capacity requirement due to its limited scalability and high energy consumption. Compared to DRAM, PCM （phase change memory） has better scalability, lower energy leakage, and non-volatility. PCM memory systems have become a hot topic of academic and industrial research. However, PCM technology has the following three drawbacks： long write latency, limited write endurance, and high write energy, which raises challenges to its adoption in practice. This paper surveys architectural research work to optimize PCM memory systems. First, this paper introduces the background of PCM. Then, it surveys research efforts on PCM memory systems in performance optimization, lifetime improving, and energy saving in detail, respectively. This paper also compares and summarizes these techniques from multiple dimensions. Finally, it concludes these optimization techniques and discusses possible research directions of PCM memory systems in future.

关键词： phase change memory memory system performance lifetime energy

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Parallel Incremental Frequent Itemset Mining for Large Data

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Journal of computer Science & technology 2017年第2期32卷 368-385页

作者： Yu-Geng Song Hui-Min Cui Xiao-Bing Feng State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China

Frequent itemset mining （FIM） is a popular data mining issue adopted in many fields, such as commodity recommendation in the retail industry, log analysis in web searching, and query recommendation （or related search）. A large number of FIM algorithms have been proposed to obtain better performance, including parallelized algorithms for processing large data volumes. Besides, incremental FIM algorithms are also proposed to deal with incremental database updates. However, most of these incremental algorithms have low parallelism, causing low efficiency on huge databases. This paper presents two parallel incremental FIM algorithms called IncMiningPFP and IncBuildingPFP, implemented on the MapReduce framework. IncMiningPFP preserves the FP-tree mining results of the original pass, and utilizes them for incremental calculations. In particular, we propose a method to generate a partial FP-tree in the incremental pass, in order to avoid unnecessary mining work. Further, some of the incremental parallel tasks can be omitted when the inserted transactions include fewer items. IncbuildingPFP preserves the CanTrees built in the original pass, and then adds new transactions to them during the incremental passes. Our experimental results show that IncMiningPFP can achieve significant speedup over PFP （Parallel FPGrowth） and a sequential incremental algorithm （CanTree） in most cases of incremental input database, and in other cases IncBuildingPFP can achieve it.

关键词： incremental parallel FPGrowth data mining frequent itemset mining MapReduce

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Continual Reinforcement Learning for Digital Twin Synchronization Optimization

arXiv

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arXiv 2025年

作者： Tong, Haonan Chen, Mingzhe Zhao, Jun Hu, Ye Yang, Zhaohui Liu, Yuchen Yin, Changchuan The Beijing Key Laboratory of Network System Architecture and Convergence The Beijing Advanced Information Network Laboratory Beijing University of Posts and Telecommunications Beijing China Singapore The Department of Electrical and Computer Engineering Frost Institute for Data Science and Computing University of Miami Coral GablesFL33146 United States The Department of Industrial and Systems Engineering University of Miami Coral GablesFL33146 United States The College of Information Science and Electronic Engineering Zhejiang University Zhejiang Hangzhou310027 China The Department of Computer Science North Carolina State University RaleighNC27695 United States The Beijing Key Laboratory of Network System Architecture and Convergence China The Beijing Advanced Information Network Laboratory Beijing University of Posts and Telecommunications Beijing100876 China

This article investigates the adaptive resource allocation scheme for digital twin (DT) synchronization optimization over dynamic wireless networks. In our considered model, a base station (BS) continuously collects factory physical object state data from wireless devices to build a real-time virtual DT system for factory event analysis. Due to continuous data transmission, maintaining DT synchronization must use extensive wireless resources. To address this issue, a subset of devices is selected to transmit their sensing data, and resource block (RB) allocation is optimized. This problem is formulated as a constrained Markov process (CMDP) problem that minimizes the long-term mismatch between the physical and virtual systems. To solve this CMDP, we first transform the problem into a dual problem that refines RB constraint impacts on device scheduling strategies. We then propose a continual reinforcement learning (CRL) algorithm to solve the dual problem. The CRL algorithm learns a stable policy across historical experiences for quick adaptation to dynamics in physical states and network capacity. Simulation results show that the CRL can adapt quickly to network capacity changes and reduce normalized root mean square error (NRMSE) between physical and virtual states by up to 55.2%, using the same RB number as traditional methods. © 2025, CC BY-NC-SA.

关键词： Markov processes

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Design for Testability Features of Godson-3 Multicore Microprocessor

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Journal of computer Science & technology 2011年第2期26卷 302-313页

作者：齐子初刘慧李向库胡伟武 Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Chinese Academy of Sciences Loongson Technologies Corporation Limited

This paper describes the design for testability （DFT） challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar （SMOC） on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism （TAM） is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

关键词： DFT （design for testability） TAM （test access mechanism） multicore processor low power test

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Memory Efficient Two-Pass 3D FFT Algorithm for Intel~ Xeon Phi^(TM) Coprocessor

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Journal of computer Science & technology 2014年第6期29卷 989-1002页

作者：刘益群李焱张云泉张先轶 Institute of Software Chinese Academy of Sciences University of Chinese Academy of Sciences Department of Computer Science and Technology Tsinghua University CCF ACM IEEE State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences

Equipped with 512-bit wide SIMD inst d large numbers of computing cores, the emerging x86-based Intel（R） Many Integrated Core （MIC） architecture ot only high floating-point performance, but also substantial off-chip memory bandwidth. The 3D FFT （three-di fast Fourier transform） is a widely-studied algorithm; however, the conventional algorithm needs to traverse the three times. In each pass, it computes multiple 1D FFTs along one of three dimensions, giving rise to plenty of rided memory accesses. In this paper, we propose a two-pass 3D FFT algorithm, which mainly aims to reduce of explicit data transfer between the memory and the on-chip cache. The main idea is to split one dimension into ensions, and then combine the transform along each sub-dimension with one of the rest dimensions respectively erence in amount of TLB misses resulting from decomposition along different dimensions is analyzed in detail. el parallelism is leveraged on the many-core system for a high degree of parallelism and better data reuse of loc On top of this, a number of optimization techniques, such as memory padding, loop transformation and vectoriz employed in our implementation to further enhance the performance. We evaluate the algorithm on the Intel（R） PhiTM coprocessor 7110P, and achieve a maximum performance of 136 Gflops with 240 threads in offload mode, which ts the vendor-specific Intel（R）MKL library by a factor of up to 2.22X.

关键词： 3D-FFT memory efficie many-core Many Integrated Core Intel（R） Xeon PhiTM

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HTDet:A Clustering Method Using Information Entropy for Hardware Trojan Detection

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Tsinghua Science and technology 2021年第1期26卷 48-61页

作者： Renjie Lu Haihua Shen Zhihua Feng Huawei Li Wei Zhao Xiaowei Li the University of Chinese Academy of Sciences Beijing 101408China Beijing Institute of Computer Technology and Application Beijing 100854China the State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China

Hardware Trojans(HTs)have drawn increasing attention in both academia and industry because of their significant potential *** this paper,we propose HTDet,a novel HT detection method using information entropybased *** maintain high concealment,HTs are usually inserted in the regions with low controllability and low observability,which will result in that Trojan logics have extremely low transitions during the *** implies that the regions with the low transitions will provide much more abundant and more important information for HT *** HTDet applies information theory technology and a density-based clustering algorithm called Density-Based Spatial Clustering of Applications with Noise(DBSCAN)to detect all suspicious Trojan logics in the circuit under *** DBSCAN is an unsupervised learning algorithm,that can improve the applicability of *** addition,we develop a heuristic test pattern generation method using mutual information to increase the transitions of suspicious Trojan *** on circuit benchmarks demonstrate the effectiveness of HTDet.

关键词： Hardware Trojan(HT)detection information entropy Density-Based Spatial Clustering of Applications with Noise(DBSCAN) unsupervised learning clustering mutual information test patterns generation

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