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The Godson Processors:Its Research,Development,and Contributions

Journal of computer Science & Technology 2011年第3期26卷 363-372页

作者：胡伟武高燕萍陈天石肖俊华 Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Loongson Technologies Corporation Limited Graduate University of Chinese Academy of Sciences

The Godson project with an R＆D history of 10 years is an independent national program of China that aims at developing advanced microprocessor technologies based on fundamental research and commercialization of the chip technology. We will give a comprehensive presentation of the Godson project, including its history, technical roadmaps, and several unique technical merits.

关键词： IT industry CPU research and development Godson microprocessor XPU system on chip

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High Performance General-Purpose Microprocessors： Past and Future

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Journal of computer Science & Technology 2006年第5期21卷 631-640页

作者：胡伟武侯锐肖俊华章隆宾 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 P.R. China

It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to simple, and new innovative architecture will emerge to utilize the continuously increasing transistor budgets. The growing importance of wire delays, changing workloads, power consumption, and design/verification complexity will drive the forthcoming era of Chip Multiprocessors （CMPs）. Furthermore, typical CMP projects both from industries and from academics are investigated. Through going into depths for some primary theoretical and implementation problems of CMPs, the great challenges and opportunities to future CMPs are presented and discussed. Finally, the Godson series microprocessors designed in China are introduced.

关键词： high performance general-purpose microprocessor instruction level parallelism data level parallelism thread level parallelism chip multiprocessors Godson processor

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Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment

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Journal of computer Science & Technology 2007年第5期22卷 673-680页

作者：王伟胡瑜韩银和李晓维张佑生 School of Computer and Information Hefei University of Technology Hefei 230009China Key Laboratory of Computer System and ArchitectureInstitute of Computing TechnologyChinese Academy of Sciences Beijing 100080China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080China School of Computer and Information Hefei University of Technology Hefei 230009China

It is a well-known fact that test power consumption may exceed that during functional operation. Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor （CMOS） circuits during test has become a significant part of the total power dissipation. Hence, it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test, to increase test reliability and to reduce test cost. This paper analyzes leakage current and presents a kind of leakage current simulator based on the transistor stacking effect. Using it, we propose techniques based on don＇t care bits （denoted by Xs） in test vectors to optimize leakage current in integrated circuit （IC） test by genetic algorithm. The techniques identify a set of don＇t care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector （MLV）. Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage,

关键词： leakage current don't care bits minimum leakage vector leakage power

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A risk-averse two-stage stochastic programming approach for backup rolling stock allocation and metro train rescheduling under uncertain disturbances

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Transportation Research Part B: Methodological 2025年 196卷

作者： Su, Boyi D'Ariano, Andrea Su, Shuai Wang, Zhikai Tessitore, Marta Leonina Tang, Tao State Key Laboratory of Advanced Rail Autonomous Operation Beijing Jiaotong University Beijing100044 China School of Automation and Intelligence Beijing Jiaotong University Beijing100044 China Frontiers Science Center for Smart High-speed Railway System Beijing Jiaotong University Beijing100044 China Department of Civil Computer Science and Aeronautical Technologies Engineering Roma Tre University Rome00146 Italy

Disturbances occur inevitably during daily operations of the metro system, leading to train delays and low service quality. Different from common deterministic reactive train rescheduling frameworks, taking the inherent uncertain characteristic of disturbance into account, this paper formulates a two-stage stochastic programming model to address the integration of proactive backup rolling stock allocation and reactive train rescheduling. Specifically, the backup rolling stock allocation plan is optimized in the first stage, while the train timetable and rolling stock circulation are rescheduled under different disturbance realizations in the second stage. The objective is to achieve a balance between allocation costs and negative disturbance impacts, which is evaluated by the mean-conditional value-at-risk criterion on account of the risk-averse attitude of train dispatchers. For computational tractability, the proposed model is reformulated as an equivalent mixed-integer linear programming (MILP) model. To improve computational efficiency, an innovative solution framework is designed. The integer L-shaped method is used to decompose the MILP into a master problem and a series of subproblems, with three acceleration techniques introduced to expedite the subproblem-solving process. Finally, numerical experiments are carried out based on the Beijing Batong Metro Line to verify the performance of the proposed mathematical model and solution framework. The results indicate that the proposed method outperforms benchmarks. Furthermore, comprehensive analysis is conducted on the effects of different parameter settings to provide some managerial insights for dispatchers. © 2025 Elsevier Ltd

关键词： Stochastic systems

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Design for Testability Features of Godson-3 Multicore Microprocessor

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Journal of computer Science & Technology 2011年第2期26卷 302-313页

作者：齐子初刘慧李向库胡伟武 Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Chinese Academy of Sciences Loongson Technologies Corporation Limited

This paper describes the design for testability （DFT） challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar （SMOC） on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism （TAM） is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

关键词： DFT (design for testability) TAM (test access mechanism) multicore processor low power test

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Dawning Nebulae:A PetaFLOPS Supercomputer with a Heterogeneous Structure

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Journal of computer Science & Technology 2011年第3期26卷 352-362页

作者：孙凝辉邢晶霍志刚谭光明熊劲李波马灿 Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences

Dawning Nebulae is a heterogeneous system composed of 9280 multi-core x86 CPUs and 4640 NVIDIA Fermi GPUs. With a Linpack performance of 1.271 petaFLOPS, it was ranked the second in the TOP500 List released in June 2010. In this paper, key issues in the system design of Dawning Nebulae are introduced. system tuning methodologies aiming at petaFLOPS Linpack result are presented, including algorithmic optimization and communication improvement. The design of its file I/O subsystem, including HVFS and the underlying DCFS3, is also described. Performance evaluations show that the Linpack efficiency of each node reaches 69.89%, and 1024-node aggregate read and write bandwidths exceed 100 GB/s and 70 GB/s respectively. The success of Dawning Nebulae has demonstrated the viability of CPU/GPU heterogeneous structure for future designs of supercomputers.

关键词： supercomputer heterogeneous systems performance evaluation

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A General-Purpose Many-Accelerator architecture Based on Dataflow Graph Clustering of Applications

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Journal of computer Science & Technology 2014年第2期29卷 239-246页

作者：陈鹏张磊韩银和陈云霁 State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

The combination of growing transistor counts and limited power budget within a silicon die leads to the utilization wall problem （a.k.a. ＂Dark Silicon＂）, that is only a small fraction of chip can run at full speed during a period of time. Designing accelerators for specific applications or algorithms is considered to be one of the most promising approaches to improving energy-efficiency. However, most current design methods for accelerators are dedicated for certain applications or algorithms, which greatly constrains their applicability. In this paper, we propose a novel general-purpose many-accelerator architecture. Our contributions are two-fold. Firstly, we propose to cluster dataflow graphs （DFGs） of hotspot basic blocks （BBs） in applications. The DFG clusters are then used for accelerators design. This is because a DFC is the largest program unit which is not specific to a certain application. We analyze 17 benchmarks in SPEC CPU 2006, acquire over 300 DFGs hotspots by using LLVM compiler tool, and divide them into 15 clusters based on graph similarity. Secondly, we introduce a function instruction set architecture （FISC） and illustrate how DFG accelerators can be integrated with a processor core and how they can be used by applications. Our results show that the proposed DFG clustering and FISC design can speed up SPEC benchmarks 6.2X on average.

关键词： dataflow graph many-accelerator clustering function instruction set architecture

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Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach

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Science China(Information Sciences) 2018年第11期61卷 31-47页

作者： Xiaowei LI Guihai YAN Jing YE Ying WANG State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

If your computer crashes, you can revive it by a reboot, an empirical solution that usually turns out to be effective. The rationale behind this solution is that transient faults, either in hardware or software,can be fixed by refreshing the machine state. Such a "silver bullet", however, could be futile in the future because the faults, especially those existing in the hardware such as Integrated Circuit(IC) chips, cannot be eliminated by refreshing. What we need is a more sophisticated mechanism to steer the system back to the right track. The "magic cure" is the Fault Tolerance On-Chip(FTOC) mechanism, which relies on a suite of built-in design-for-reliability logic, including fault detection, fault diagnosis, and error recovery, working in a self-supportive manner. We have exploited the FTOC to build a holistic solution ranging from on-chip fault detection to error recovery mechanisms to address faults caused by chips progressively aging. Besides fault detection, the FTOC paradigm provides attractive benefits, such as facilitating graceful performance degradation, mitigating the impact of verification blind spots, and improving the chip yield.

关键词： fault tolerance on-chip self-test self-diagnosis self-repair

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Reinventing Memory system Design for Many-Accelerator architecture

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Journal of computer Science & Technology 2014年第2期29卷 273-280页

作者：王颖张磊韩银和李华伟 State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

The many-accelerator architecture, mostly composed of general-purpose cores and accelerator-like function units （FUs）, becomes a great alternative to homogeneous chip multiprocessors （CMPs） for its superior power-efficiency. However, the emerging many-accelerator processor shows a much more complicated memory accessing pattern than general purpose processors （GPPs） because the abundant on-chip FUs tend to generate highly-concurrent memory streams with distinct locality and bandwidth demand. The disordered memory streams issued by diverse accelerators exhibit a mutual- interference behavior and cannot be efficiently handled by the orthodox main memory interface that provides an inflexible data fetching mode. Unlike the traditional DRAM memory, our proposed Aggregation Memory system （AMS） can function adaptively to the characterized memory streams from different FUs, because it provides the FUs with different data fetching sizes and protects their locality in memory access by intelligently interleaving their data to memory devices through sub-rank binding. Moreover, AMS can batch the requests without sub-rank conflict into a read burst with our optimized memory scheduling policy. Experimental results from trace-based simulation show both conspicuous performance boost and energy saving brought by AMS.

关键词： many-accelerator chip multiprocessor memory general purpose processor

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MIMS:Towards a Message Interface Based Memory system

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Journal of computer Science & Technology 2014年第2期29卷 255-272页

作者：陈荔城陈明宇阮元黄永兵崔泽汉卢天越包云岗 State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

The decades-old synchronous memory bus interface has restricted many innovations in the memory system, which is facing various challenges （or walls） in the era of multi-core and big data. In this paper, we argue that a message- based interface should be adopted to replace the traditional bus-based interface in the memory system. A novel message interface based memory system called MIMS is proposed. The key innovation of MIMS is that processors communicate with the memory system through a universal and flexible message packet interface. Each message packet is allowed to encapsulate multiple memory requests （or commands） and additional semantic information. The memory system is more intelligent and active by equipping with a local buffer scheduler, which is responsible for processing packets, scheduling memory requests, preparing responses, and executing specific commands with the help of semantic information. Under the MIMS framework, many previous innovations on memory architecture as well as new optimization opportunities such as address compression and continuous requests combination can be naturally incorporated. The experimental results on a 16-core cycle-detailed simulation system show that： with accurate granularity message, MIMS can improve system performance by 53.21% and reduce energy delay product （EDP） by 55.90%. Furthermore, it can improve effective bandwidth utilization by 62.42% and reduce memory access latency by 51% on average.

关键词： message interface memory system asynchronous granularity semantic information

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