检索结果-内蒙古大学图书馆

2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Li Ding Ping Kang Wenbo Yin Zhi-Hua Feng State Key Laboratory of ASIC & System Fudan University Beijing Institute of Computer Technology and Application

ISBN: (纸本)9781467397209

With the data growth related to the increase of devices with network access, the high speed Ethernet is widely used in various fields from big data center to high frequency transaction(HFT). However, the conventional software-based protocol stack consumes large amount of CPU time at full transmission rate, and leads to low performance such as high latency and low throughput. This paper presents a hardware based TCP offload engine(TOE) operating at full 10 Gbps throughput full-duplex with the low latency. Features supporting high speed network such as congestion avoidance and timestamp are implemented. The proposed TOE is verified by interacting with the software protocol stack. The performance measurement shows our TOE can provide transmission rate up to 10 Gbps as both transmitter and receiver. The input-to-output latency for 100 bytes payload and 64 bytes header with timestamp is about 90 nanoseconds compared with the 140 nanoseconds implemented by Dini Group.

关键词： Design and Implementation of Hardware-Based Low Latency TCP Offload Engine for 10 Gbps Ethernet TOE Engine

来源：评论

学校读者我要写书评

暂无评论

Shipping Economics Development:A Review from the Perspective of the Shipping Industry Chain for the Past Four Decades

引用

Journal of Shanghai Jiaotong university(Science) 2022年第3期27卷 424-436页

作者： XIA Qiliang CHEN Feier State Key Laboratory of Ocean Engineering School of Naval ArchitectureOcean and Civil EngineeringKey Laboratory of Marine Intelligent Equipment and System of Ministry of EducationShanghai Jiao Tong UniversityShanghai 200240China

To know the development of shipping economics,it is meaningful to overview shipping economics systemically from the perspective of markets and the shipping industry *** stimulate future research,this article presents an introduction to the evolution of research models including static models,dynamic models and networks theory,the characteristics of shipping markets including volatility,seasonal and market cycle,and a comprehensive review of the development of shipping economics in the past four *** review shipping economics in the following steps:single market’s research is generalized including the freight market,financial market including FFA market and investment market,shipbuilding market,and secondhand market;two markets’correlation,information transmission,spillover effects,and other rules in shipping markets are surveyed;the correlation and risk of multi-markets are also ***,we summarize relationships of the shipping industry ***,we figure out issues in this field that need further study.

关键词： shipping economics market characteristics single market shipping industry chain

来源：评论

学校读者我要写书评

暂无评论

Frequency stability enhancement of a two-area interconnected power system under error-based active disturbance rejection control

引用

Measurement 2025年 254卷

作者： Dawei Pang Tianmu Qin Ming Du Yuguang Niu State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources School of Control and Computer Engineering North China Electric Power University Beijing 102206 China Beijing Huairou Laboratory Beijing 101400 China

In the context of grid-connected renewable energy sources and deep peak shaving of thermal power units, the grid structure and characteristics are variable. In this regard, the application of error-based active disturbance rejection control (EADRC) in a two-area interconnected power system is considered with the aim of enhancing the frequency stability of the system. The stability of the proposed strategy is demonstrated and the effects of load variations and renewable energy output fluctuations on frequency are analyzed by modeling the two-area power system. Meanwhile, a comparison of control strategies of different orders is carried out. Simulation results show that the use of EADRC technique under NSGA-II rectification significantly improves the frequency response, both in terms of error and output smoothness. The effectiveness of the proposed strategy is verified in the IEEE 39-Bus system. The proper controller order selection and disturbance rejection core idea are beneficial to enhance the overall frequency stability of the power system.

关键词： Disturbance rejection

来源：评论

学校读者我要写书评

暂无评论

Circuit implementation of floating point range reduction for trigonometric functions

Circuit implementation of floating point range reduction for...

引用

2007 IEEE International Symposium on Circuits and systems, ISCAS 2007

作者： Xuehai, Qian Hao, Zhang Jingang, Yang He, Huang Junchao, Zhang Dongrui, Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Range reduction is important in evaluating trigonometric functions but not enough work is done in relation to the hardware implementation of it. A hardware floating point range reduction implementation is presented. The whole reduction is divided into two steps;the first is based on Double-Residue modular range reduction method and the second adopts on a novel method described in this paper. The latter one can reduce the argument to an arbitrary range and provides the number of times that range constant contained in the argument It has been synthesized using 0.13 um library to achieve an approximately 700 MHz operation frequency. © 2007 IEEE.

关键词： Digital circuits

来源：评论

学校读者我要写书评

暂无评论

Cs 455nm Nonlinear Spectroscopy with Ultra-narrow Linewidth

引用

Chinese Physics Letters 2013年第6期30卷 50-52页

作者： WANG Dong-Ying WANG Yan-Fei TAO Zhi-Ming ZHANG Sheng-Nan HONG Ye-Long ZHUANG Wei CHEN Jing-Biao State Key Laboratory of Advanced Optical Communication System and Network Institute of Quantum ElectronicsSchool of Electronics Engineering&Computer SciencePeking UniversityBeijing 100871

Nonlinear spectroscopy has become a useful tool in laser cooling,frequency stabilization and so *** use the 455.5 nm light beam output of an external cavity diode laser to perform the saturation spectroscopy signal and polarization spectroscopy signal on the 6S_(1/2)→7P3/2 transition in *** measured linewidth of the F4→4,5 transition is as narrow as 1.40 MHz and that of the F3→2,3 transition is 1.67 *** of them are very close to the natural linewidth of about 1.2 *** result is the narrowest measured linewidth of Cs 455 nm saturation spectroscopy signal to our knowledge.

关键词： polarization narrow signal

来源：评论

学校读者我要写书评

暂无评论

A Fast HDL Model for Full-Custom FPGA Verification 12

A Fast HDL Model for Full-Custom FPGA Verification

引用

2017 IEEE 12th International Conference on ASIC

作者： Kaixuan Zhang Zhihua Feng Hao Zhou State Key Laboratory of ASIC & System Fudan University Beijing Institute of Computer Technology and Application

ISBN: (纸本)9781509066261;9781509066254

Verification occupies an important role in design of full-custom Field Programmable Gate Array(FPGA).In general,a full-custom FPGA is manually designed in the transistor ***,it is normally too slow for conventional Electronic Design Automation(EDA) software to run the full-chip transistor-level simulation and verification *** order to solve this problem,we propose a methodology to build a fast Hardware Description Language(HDL) model for FPGA,which can then be simulated by EDA tools in the multi-core mode efficiently and *** build an automatic platform based on the methodology to generate the HDL model and a verification platform to realize a fast and convenient functional verification for a full-custom *** an experiment,an internally developed twenty-million-transistor FDP FPGA [1] is used to verify the efficiency of the *** our experiment,it takes 3.65 h to verify the model of the internally developed twenty-million-transistor FPGA with 32-core simulation.

关键词： A Fast HDL Model for Full-Custom FPGA Verification HDL Model

来源：评论

学校读者我要写书评

暂无评论

GenerOS: An asymmetric operating system kernel for multi-core systems

GenerOS: An asymmetric operating system kernel for multi-cor...

引用

24th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2010

作者： Yuan, Qingbo Zhao, Jianbo Chen, Mingyu Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Compute Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424464432

Due to complex abstractions implemented over shared data structures protected by locks, conventional symmetric multithreaded operating system kernel such as Linux is hard to achieve high scalability on the emerging multi-core architectures, which integrate more and more cores on a single die. This paper presents GenerOS - a general asymmetric operating system kernel for multi-core systems. In principal, GenerOS partitions processing cores into application core, kernel core and interrupt core, each of which is dedicated to a specified function. In implementation, we conduct a delicate modification to Linux kernel and provide the same interface as Linux kernel so that GenerOS is compatible with legacy applications. The better performance of GenerOS mainly benefits from: (1) Applications run on their own cores with minimal interrupt and kernel support;(2) Every kernel service is encapsulated into a serial process so that there will be fewer contentions than conventional symmetric kernel;(3) A slim schedule policy is used in the kernel core to support schedule between system calls with low overhead. Experiments with two typical workloads on 16-core AMD machine show that GenerOS behaves better than original Linux kernel when there are more processing cores (19.6% for TPCH using oracle database management system and 42.8% for httperf using apache web server). © 2010 IEEE.

关键词： Linux

来源：评论

学校读者我要写书评

暂无评论

Virtual resource monitoring in cloud computing

引用

Journal of Shanghai University(English Edition) 2011年第5期15卷 381-385页

作者：韩芳芳彭俊杰张武李青李建敦江钦龙袁勤 School of Computer Engineering and Science Shanghai University Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Science

Cloud computing is a new computing model. The resource monitoring tools are immature compared to traditional distributed computing and grid computing. In order to better monitor the virtual resource in cloud computing, a periodically and event-driven push （PEP） monitoring model is proposed. Taking advantage of the push and event-driven mechanism, the model can provide comparatively adequate information about usage and status of the resources. It can simplify the communication between Master and Work Nodes without missing the important issues happened during the push interval. Besides, we develop ＂mon＂ to make up for the deficiency of Libvirt in monitoring of virtual CPU and memory.

关键词： virtual resource monitoring cloud computing virtualization

来源：评论

学校读者我要写书评

暂无评论

Snooping and ordering ring - An efficient cache coherence protocol for ring connected CMP

Snooping and ordering ring - An efficient cache coherence pr...

引用

15th International Conference on Parallel and Distributed systems, ICPADS '09

作者： Cao, Fei Liu, Zhiyong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China

ISBN: (纸本)9780769539003

Ring is a promising on-chip interconnection for CMP. It is more scalable than bus and much simpler than packet-switched networks. The ordering property of ring can be used to optimize cache coherence protocol design. Existing ring protocols, such as the snooping ring protocol and the ring-order protocol need a retry and acknowledgement scheme or use the ordering property of the ring respectively to resolve conflict memory requests. A cache coherence protocol named SOR (Snooping and Ordering Ring) is developed for ring connected CMP in this paper. This protocol is based on the snooping ring protocol. But instead of using the acknowledgement and retry scheme, it uses the ordering property of the ring to resolve conflicts, thus can avoid unnecessary retries to improve performance and power efficiency. The L1 snooping results are sent with the requests instead of being delayed, so that many useless snoops can be avoided. Simulation result shows that the average probe slot transports and snoop operations can be reduced by SOR are 47% and 48.9%. The average and maximum performance improvements by SOR are 3.33% and 6%. © 2009 IEEE.

关键词： Packet switching

来源：评论

学校读者我要写书评

暂无评论

A Non-Stop Double Buffering Mechanism for Dataflow architecture

引用

Journal of computer Science & Technology 2018年第1期33卷 145-157页

作者： Xu Tan Xiao-Wei Shen Xiao-Chun Ye Da Wang Dong-Rui Fan Lunkai Zhang Wen-Ming Li Zhi-Min Zhang Zhi-Min Tang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing 100049 China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi 214125 China Department of Computer Science The University of Chicago Chicago IL 60637 U.S.A.

Double buffering is an effective mechanism to hide the latency of data transfers between on-chip and off-chip memory. However, in dataflow architecture, the swapping of two buffers during the execution of many tiles decreases the performance because of repetitive filling and draining of the dataflow accelerator. In this work, we propose a non-stop double buffering mechanism for dataflow architecture. The proposed non-stop mechanism assigns tiles to the processing element array without stopping the execution of processing elements through optimizing control logic in dataflow architecture. Moreover, we propose a work-flow program to cooperate with the non-stop double buffering mechanism. After optimizations both on control logic and on work-flow program, the filling and draining of the array needs to be done only once across the execution of all tiles belonging to the same dataflow graph. Experimental results show that the proposed double buffering mechanism for dataftow architecture achieves a 16.2% average efficiency improvement over that without the optimization.

关键词： non-stop double buffering dataflow architecture high-performance computing

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：