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Capacity Allocation of Renewable Energy Sources Considering Complementarity

CSEE Journal of Power and Energy systems 2024年第4期10卷 1415-1426页

作者： Yinzhe Hu Kaigui Xie Bo Hu Hengming Tai Changzheng Shao Chunyan Li Xueying Yu State Key Laboratory of Power Transmission Equipment and System Security at the Chongqing University Chongqing 400030China Department of Electrical and Computer Engineering University of TulsaTulsaOK 74104USA

The outputs of renewable energy sources(RESs)are inherently variable and uncertain,such as wind power(WP)and photovoltaic(PV).However,the outputs of various types of RESs in different regions are *** the capacity of RESs could be properly allocated during system planning,variability of the total output could be ***,system reliability and renewable energy(RE)consumption could be *** paper proposes an analytical model for optimal complementary capacity allocation of RESs to decrease variability of the total *** model considers the capacity ratio of RESs as decision variables and the coefficient of variation(CV)of the total output as the objective *** proposed approach transforms the single-level optimization model into a bilevel optimization model and derives an analytical equation that can directly calculate the optimal complementary capacity ratio(OCCR)of system *** studies on wind and solar farms in Xinjiang and Qinghai,China,are performed to verify the effectiveness of the proposed analytical allocation method.

关键词： Analytical equation capacity allocation complementary optimization renewable energy variability

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DoCE: Direct extension of on-chip interconnects over converged ethernet for rack-scale memory sharing 1

DoCE: Direct extension of on-chip interconnects over converg...

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1st Workshop on Emerging Technologies for Software-Defined and Reconfigurable Hardware-Accelerated Cloud Datacenters, ETCD 2017 - Held in conjunction with 22nd ACM ASPLOS

作者： Chang, Yisong Zhao, Ran Yu, Lei Zhang, Ke State Key Laboratory of Computer Architecture ICT CAS Beijing100190 China

ISBN: (纸本)9781450349239

Novel rack-level interconnects are urgently required to support frequent inter-server communications in emerging large-scale distributed in-memory applications. In this paper, we introduce DoCE, a memory semantic fabric via Direct extension of on-chip interconnect (DEOI) over Converged Ethernet. Based on the architectural support for fine-grained remote memory sharing, DoCE provides a 9.6x speedup for distributed implementation of PageRank algorithm on our dual-node ARM SoC-FPGA prototype versus a conventional TCP/IP based solution. To the best of our knowledge, DoCE is the first implementation and prototype for memory semantic fabric via existing Ethernet infrastructure in ARM ecosystem. © 2016 ACM.

关键词： Ethernet

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IMPULP:A Hardware Approach for In-Process Memory Protection via User-Level Partitioning

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Journal of computer Science & Technology 2020年第2期35卷 418-432页

作者： Yang-Yang Zhao Ming-Yu Chen Yu-Hang Liu Zong-Hao Yang Xiao-Jing Zhu Zong-Hui Hong Yun-Ge Guo State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China Peng Cheng Laboratory Shenzhen 518055China

In recent years many security attacks occur when malicious codes abuse in-process memory *** to the increasing complexity,an application program may call third-party code which cannot be controlled by programmers but may contain security *** a result,the users have the risk of suffering information leakage and control flow ***,current solutions like Intel memory protection extensions(MPX)severely degrade performance,while other approaches like Intel memory protection keys(MPK)lack flexibility in dividing security *** this paper,we propose IMPULP,an effective and efficient hardware approach for in-process memory *** rationale of IMPULP is user-level partitioning that user code segments are divided into different security domains according to their instruction addresses,and accessible memory spaces are specified dynamically for each domain via a set of boundary *** instruction related to memory access will be checked according to its security domain and the corresponding boundaries,and illegal in-process memory access of untrusted code segments will be *** can be leveraged to prevent a wide range of in-process memory abuse attacks,such as buffer overflows and memory *** verification,an FPGA prototype based on RISC-V instruction set architecture has been *** present eight tests to verify the effectiveness of IMPULP,including five memory protection function tests,a test to defense typical buffer overflow,a test to defense famous memory leakage attack named Heartbleed,and a test for security *** execute the SPEC CPU2006 benchmark programs to evaluate the efficiency of *** performance overhead of IMPULP is less than 0.2%runtime on average,which is ***,the resource overhead is less than 5.5%for hardware modification of IMPULP.

关键词： in-process isolation memory protection out-of-bounds user-level partitioning

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Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology

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Journal of computer Science & Technology 2007年第1期22卷 1-14页

作者：胡伟武赵继业钟石强杨旭 Elio Guidetti 吴永强 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China ST Microelectronics 39 Chemin du Camp-des-Filles 1228 Plan Les Ouates Geneva Switzerland

This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bitsliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.

关键词： general-purpose processor superscalar pipeline out-of-order execution non-blocking cache physical design,synthesis flow bit-sliced placement crafted cell performance evaluation

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Assessment and Enhancement of FRC of Power systems Considering Thermal Power Dynamic Conditions

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CSEE Journal of Power and Energy systems 2024年第4期10卷 1371-1383页

作者： Feng Hong Yalei Pang Weiming Ji Lu Liang Fang Fang Junhong Hao Jizhen Liu State Key Laboratory of Alternate Electric Power System with Renewable Energy Sources and School of Control and Computer Engineering North China Electric Power UniversityBeijing 102206China State Key Laboratory of Alternate Electric Power System with Renewable Energy Sources School of Energy Power and Mechanical EngineeringNorth China Electric Power UniversityBeijing 102206China

Frequency stability and security have been a vital challenge as large-scale renewable energy is integrated into power *** contrast,the proportion of traditional thermal power units decreases during the decarbonization transformation process,resulting in poor frequency *** paper aims to explore the potential of frequency regulation support,dynamic assessment,and capacity promotion of thermal power plants in the transition *** the dynamic characteristics of the main steam working fluid under different working conditions,a nonlinear observer is constructed by extracting the main steam pressure and valve opening degree *** real-time frequency modulation capacity of thermal power units can provide a dynamic state for the power grid.A dynamic adaptive modification for primary frequency control(PFC)of power systems,including wind power and thermal power,is proposed and *** power dynamic allocation factor is adaptively optimized by predicting the speed droop ratio,and the frequency modulation capability of the system is improved by more than 11%under extreme ***,through the Monte Carlo simulation of unit states of the system under various working conditions,the promotion of the frequency regulation capacity with high wind power penetration(WPP)is verified.

关键词： Dynamic evaluation frequency regulation power system predictive modeling wind penetration

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A study and implementation of the Huffman algorithm based on condensed Huffman table

A study and implementation of the Huffman algorithm based on...

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International Conference on computer Science and Software Engineering, CSSE 2008

作者： Bao, Ergude Li, Weisheng Fan, Dongrui Ma, Xiaoyu School of Software Beijing Jiaotong University Key Laboratory of Computer System and Architecture Institute of Computer Technology Chinese Academy of Sciences

ISBN: (纸本)9780769533360

Huffman codes are being widely used as a very efficient technique for compressing data. To achieve high compressing ratio, some properties of encoding and decoding for canonical Huffman table are discussed. A study and implementation of the Huffman algorithm based on condensed Huffman table is studied. New condensed Huffman table could reduce the cost of the Huffman coding table. Compared with traditional Huffman coding table and other improved tables, the best advantages of new condensed Huffman table is that the space requirement is reduced significantly. © 2008 IEEE.

关键词： Codes (symbols)

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Will the fibers of the future be considered fibers?

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National Science Review 2024年第10期11卷 15-17页

作者： Dewen Xu Ya Liu Hailiang Wang Wei Yan Changjun Jiang Meifang Zhu State Key Laboratory for Modification of Chemical Fibers and Polymer Materials College of Materials Science and Engineering Donghua University Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Department of Computer Science and Technology Tongji University

Fiber materials are key materials that have changed human history and promoted the progress of human civilization. In ancient times, humans used feathers and animal skins for clothing, and later they widely employed natural fibers such as cotton, hemp, silk and wool to make fabrics(Fig. 1a). Chinese ancestors had mastered the art of natural fiber weaving as early as the Neolithic *** thousand years ago, people were already familiar with and adept at techniques for spinning natural fibers [1].

关键词： future will considered fibers

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Temperature-switching logic in MoS2 single transistors

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Chinese Physics B 2020年第9期29卷 464-469页

作者： Xiaozhang Chen Lehua Gu Lan Liu Huawei Chen Jingyu Li Chunsen Liu Peng Zhou The State Key Laboratory of ASIC and System Department of MicroelectronicsFudan UniversityShanghai 200433China Department of Physics State Key Laboratory of Surface PhysicsKey Laboratory of Micro and Nano Photonic Structures(Ministry of Education)and Institute for Nanoelectronic Devices and Quantum ComputingFudan UniversityShanghai 200433China School of Computer Science Fudan UniversityShanghai 200433China

Due to their unique characteristics,two-dimensional(2D)materials have drawn great attention as promising candidates for the next generation of integrated circuits,which generate a calculation unit with a new working mechanism,called a logic *** figure out the application prospects of logic transistors,exploring the temperature dependence of logic characteristics is *** this work,we explore the temperature effect on the electrical characteristic of a logic transistor,finding that changes in temperature cause transformation in the calculation:logical output converts from‘AND’at 10 K to‘OR’at 250 *** transformation phenomenon of temperature regulation in logical output is caused by energy band which decreases with increasing *** the experiment,the indirect band gap of MoS2 shows an obvious decrease from 1.581 eV to 1.535 eV as the temperature increases from 10 K to 250 *** change of threshold voltage with temperature is consistent with the energy band,which confirms the theoretical ***,as a promising material for future integrated circuits,the demonstrated characteristic of 2D transistors suggests possible application for future functional devices.

关键词： molybdenum disulfide(MoS2) logic temperature dependence mobility

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Design of high reliability RF-LDMOS by suppressing the parasitic bipolar effect using enhanced p-well and double epitaxy

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Journal of Semiconductors 2015年第6期36卷 93-98页

作者：徐向明黄景丰遇寒钱文生周正良韩波王勇王鹏飞张卫 State Key Laboratory of ASIC and System School of Microelectronics Fudan University HuaHong Grace Semiconductor Manufacturing Corporation School of Computer and Information Engineering Fuyang Teachers College

A laterally diffused metal-oxide-semiconductor （LDMOS） device design with an enhanced p-well and double p-epitaxial structure is investigated for device ruggedness improvement while keeping its high device per- formance under high frequency. Based upon the device design, radio-frequency （RF） LDMOS transistors for GSM （global system for mobile communication） application have been fabricated by using 0.35/zm CMOS technolo- gies. Experimental data show that the proposed device achieves a breakdown voltage of 70 V, output power of 180 W. The RF linear gain is over 20 dB and the power added efficiency （PAE） is over 70% with the frequency of 920 MHz. In particular, it can pass the 20 ： 1 voltage standing wave ratio （VSWR） load mismatch biased at drain DC supply voltage of 32 V and output power at 10-dB gain compression point （P10dB）. The device ruggedness has been remarkably improved by using the proposed device structure.

关键词： RF power LDMOS semiconductor device ruggedness reliability

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New methodologies for parallel architecture

New methodologies for parallel architecture

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作者： Fan, Dong-Rui Li, Xiao-Wei Li, Guo-Jie Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Moore's law continues to grant computer architects ever more transistors in the foreseeable future, and para-llelism is the key to continued performance scaling in modern microprocessors. In this paper, the achievements in our research project, which is supported by the National Basic Research 973 Program of China, on parallel architecture, are systematically presented. The innovative approaches and techniques to solve the significant problems in parallel architecture design are summarized, including architecture level optimization, compiler and language-supported technologies, reliability, power-performance efficient design, test and verification challenges, and platform building. Two prototype chips, a multi-heavy-core Godson-3 and a many-light-core Godson-T, are described to demonstrate the highly scalable and reconfigurable parallel architecture designs. We also present some of our achievements appearing in ISCA, MICRO, ISSCC, HPCA, PLDI, PACT, IJCAI, Hot Chips, DATE, IEEE Trans. VLSI, IEEE Micro, IEEE Trans. computers, etc. © 2011 Springer Science+Business Media, LLC & Science Press, China.

关键词： Parallel architectures

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