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IEEE VLSI Test Symposium (VTS)

作者： Jianliang Gao Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences

ISBN: (纸本)9781424437696

Bugs are tending to be unavoidable in the design of complex integrated circuits. It is imperative to identify the bugs as soon as possible by post-silicon debug. The main challenge for post-silicon debug is the observability of the internal signals. This paper exploits the fact that it is not necessary to observe the error free states. Then we introduce "suspect window" and present a method for determining its boundary. Based on suspect window, we propose a debug approach to achieve high observability by reusing scan chain. Since scan dumps take place only in suspect window, debug time is greatly reduced. Experimental results demonstrate the effectiveness of the proposed approach.

关键词： Post-silicon debug Suspect window Trace Scan Bug

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A novel design of behavioral analysis capability in mobile SNS

A novel design of behavioral analysis capability in mobile S...

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2009 IEEE International Conference on Communications Technology and Applications, IEEE ICCTA2009

作者： Guangxi, Cheng Zhihan, Liu Hua, Zou Hao, Dong State Key Laboratory of Networking and Switching Beijing University of Posts and Telecommunications Beijing China System Architecture Department Communication Services RandD Institute Zhong Xing Telecommunication Equipment Company Limited China

ISBN: (纸本)9781424448203

This paper introduces a novel design of the Behavioral Analysis Capability in Mobile SNS. The capability has a basic part comprises relationship based interface, content based interface and time based interface. The basic capability can either provide APIs directly up to applications or encapsulate into advanced capability with the core of relationship based interface. Afterwards, explaining the usability of this capability through its disposition in Mobile SNS. Finally, by using basic and advanced interfaces respectively, two typical application examples represent the practicability of Behavioral Analysis Capability. ©2009 IEEE.

关键词： Application programming interfaces (API)

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Rendering method for multi-attribute objects based on state transition optimization strategy

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of computer-Aided Design and computer Graphics 2009年第3期21卷 311-318页

作者： Chen, Zhiyu Liang, Xiaohui Yu, Zhuo State Key Laboratory of Virtual Reality Technology and System School of Computer Science and Engineering Beihang University Beijing 100083 China

Efficient rendering of complex scenes has receive great attention in real-time computer graphics. Current researches are mostly concentrated on reducing the geometric complexity of the scene model such as reconstructing an LOD representation, performing visibility culling etc. However, the rendering process of complex scenes involves not only the geometric information of each object, but also multiple attributes, including lighting, material, texture, etc. The invocation of each attribute corresponds to a specific state in the rendering pipeline, frequent transfer between different states in the pipeline will introduce large amount of overhead, hence reducing the rendering efficiency. A rendering method accounting for efficient invocation of multiple attributes of objects based on state transition optimization strategies is presented. It estimates the cost for invoking each attribute of objects in the rendering pipeline and expresses the transitions between various render states as a weighted directed graph. Then the optimized sequence of state transition is obtained by optimization. Experimental results show that our proposed method can effectively reduce the overhead of state transition and improve the rendering efficiency of scenes containing large amounts of multi-attribute objects.

关键词： Efficiency

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Software and Hardware Cooperate for 1-D FFT Algorithm Optimization on Multicore Processors

Software and Hardware Cooperate for 1-D FFT Algorithm Optimi...

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International Conference on computer and Information Technology (CIT)

作者： Yongbin Zhou Junchao Zhang Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Multicore architecture is becoming a promise to keep Moore's Law and brings a revolution in both research and industry which results new design space for software and architecture. Fast Fourier transform (FFT), computing intensive and bandwidth intensive, is one of the most popular and important applications in the world. Compared with the computing resource on multicore architecture, the on-chip memory resource is much more expensive because of the limitation of physical chip size. Efficient implementation of FFT algorithm on multicore with good scalability is a challenge for both software and hardware developers. In this paper, supported by the Godson-T architecture, an optimized implementation of 1-D FFT has been developed with matrix transpose conceal and computation/communication overlapping, which achieve more than 30% performance improvement as well as almost 1/3 L2 cache consumption reduce comparing with the base six-step FFT. The limitation of scalability is also analyzed and the conclusion is that on Godson-T when frequency and simultaneous data access happen, the limited access bandwidth of L2 cache is the bottleneck and result in the longer on-chip network latency.

关键词： Hardware Software algorithms Multicore processing computer architecture Bandwidth Scalability Moore's Law Aerospace industry computer industry Software design

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Efficient binary translation system with low hardware cost

Efficient binary translation system with low hardware cost

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Weiwu Hu Qi Liu Jian Wang Songsong Cai Menghao Su Xiaoyu Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Binary translation is one of the most important approaches for system migration. However, software binary translation systems often suffer from the inefficiency and traditional hardware-software co-designed virtual machines require the unavoidable re-design of the processor architecture. This paper presents a novel hardware-software co-designed method to accelerate the binary translation on an existing architecture. The hardware supports for source-architecture-only functions, partial decodes and binary translation system acceleration are proposed. These hardware supports help the binary translation system to achieve high performance and simplify the design of the binary translation software. In the meantime, the hardware cost is well controlled in a certain low level. These supports are implemented in Godson-3 processors to speedup the x86 binary translation to the native MIPS instruction set. Performance evaluations on RTL simulation and FPGA emulation platforms show that the proposed method can speedup most benchmark programs by nearly 10 times compared to pure software-based binary translation and achieves about 70% performance of the native program execution. The chip is fabricated in ST 65nm CMOS technology, and the physical design results show that the chip area cost is less than 5%.

关键词： Hardware Costs computer architecture Acceleration CMOS technology Software systems Virtual machining Decoding Software performance Field programmable gate arrays

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Column-based RLE in row-oriented database

Column-based RLE in row-oriented database

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International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, CyberC

作者： Mingyuan An Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

In database systems, disk I/O performance is usually the bottleneck of the whole query processing. Among many techniques, compression is one of the most important ones to reduce disk accesses so to improve system performance. RLE (run-length encoding) is one light-weight compression algorithm which incurs negligible CPU cost. A lot of work show that, although RLE is one of the most effective compression techniques in column-oriented systems, it is very hard to use due to bad value locality in row-oriented systems where values from multiple attributes are stored in the same page. We propose CRLE (Column-based RLE), one compression algorithm to apply RLE to row-oriented data storage. On row-oriented storage page, CRLE can exploit value locality in individual column and encode values from the same column in run-length format. Experiments show that CRLE can lead to very good compression ratio and performance in spite of row-oriented data storage.

关键词： Database systems system performance Encoding Compression algorithms Costs Memory Engines Laboratories computer architecture Query processing

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Snooping and Ordering Ring - An Efficient Cache Coherence Protocol for Ring Connected CMP

Snooping and Ordering Ring - An Efficient Cache Coherence Pr...

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International Conference on Parallel and Distributed systems (ICPADS)

作者： Fei Cao Zhiyong Liu Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Ring is a promising on-chip interconnection for CMP. It is more scalable than bus and much simpler than packet-switched networks. The ordering property of ring can be used to optimize cache coherence protocol design. Existing ring protocols, such as the snooping ring protocol and the ring-order protocol need a retry and acknowledgement scheme or use the ordering property of the ring respectively to resolve conflict memory requests. A cache coherence protocol named SOR (Snooping and Ordering Ring) is developed for ring connected CMP in this paper. This protocol is based on the snooping ring protocol. But instead of using the acknowledgement and retry scheme, it uses the ordering property of the ring to resolve conflicts, thus can avoid unnecessary retries to improve performance and power efficiency. The L1 snooping results are sent with the requests instead of being delayed, so that many useless snoops can be avoided. Simulation result shows that the average probe slot transports and snoop operations can be reduced by SOR are 47% and 48.9%. The average and maximum performance improvements by SOR are 3.33% and 6%.

关键词： Broadcasting Bandwidth Delay Multiprocessing systems Energy consumption Access protocols Laboratories Concurrent computing Distributed computing computer architecture

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Logical clustering for fast clock skew scheduling

Logical clustering for fast clock skew scheduling

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： Liang Yang Jiye Zhao Baoxia Fan Ge Zhang Key Laboratory of Computer System and Architecture CAS I. C. T Beijing China

Clock skew scheduling (CSS) is an effective approach to improve the circuit frequency in synchronous circuits. Most previous works about CSS were based on individual registers, but they suffered from scaling problems for large designs. To alleviate this problem, we introduce a novel abstract layer called logical cluster instead of traditional register. A bounded logical clustering method based on timing relation (TRLC) is proposed to reduce the number of independent nodes, and then the tradeoff between aggregation degree and potential upper bound of optimal frequency is analyzed. Furthermore, a bus group logical clustering method (BGLC) is presented to achieve higher aggregation if additional logic information is available. Our experiments show that our approaches achieve significant reduction for the input size of CSS problem even by orders of magnitude, and derive a superlinear or even exponential speedup in runtime.

关键词： Clocks Cascading style sheets Circuits Frequency Registers Clustering methods Timing Upper bound Logic Runtime

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A Parallel Algorithm for Computing Betweenness Centrality

A Parallel Algorithm for Computing Betweenness Centrality

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International Conference on Parallel Processing (ICPP)

作者： Guangming Tan Dengbiao Tu Ninghui Sun Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

In this paper we present a multi-grained parallel algorithm for computing betweenness centrality, which is extensively used in large-scale network analysis. Our method is based on a novel algorithmic handling of access conflicts for a CREW PRAM algorithm. We propose a proper data-processor mapping, a novel edge-numbering strategy and a new triple array data structure recording the shortest path for eliminating conflicts to access the shared memory. The algorithm requires O(n+m) space and O((nm)/p) ( or O((nm+n 2 logn)/p)) time for unweighted (or weighted) graphs, and it is a work-optimal CREW PRAM algorithm. On current multi-core platforms, our algorithm outperforms the previous algorithm by 2-3 times.

关键词： Parallel algorithms Concurrent computing Proteins Phase change random access memory Complex networks Algorithm design and analysis Large-scale systems Parallel processing Fungi computer networks

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A modeling approach of mobile ad hoc networks survivability model

A modeling approach of mobile ad hoc networks survivability ...

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1st International Conference on Information Science and Engineering, ICISE2009

作者： Wang, Haiquan Ma, Xinyi Xia, Chunhe Hao, Senshen State Key Laboratory of Virtual Reality Technology and System Beihang University Beijing China Key Laboratory of Beijing Network Technology Beihang University Beijing China College of Software Beihang University Beijing China Shool of Computer Science and Engineering Beihang University Beijing China

ISBN: (纸本)9780769538877

Survivability has become a focal point of research. Simulation is a common method for experimental verification to identify the advantages and deficiencies of survivability models and architectures. This paper proposes a modeling approach of mobile ad hoc network survivability model which support the automatic transformation to a simulation instance. A new survivability model MARC based on the idea of ARC model is conducted. Within this model, the concepts of network services and events are analyzed and formally descript in details. Base on these works, we design MARCDL and outline the important EBNF in this paper. Use of this language is illustrated by a case study. ©2009 IEEE.

关键词： Mobile ad hoc networks

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