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检索条件"机构=State Key Laboratory of Computer System and Architecture"
2801 条 记 录,以下是2511-2520 订阅
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Verification Web Services Composition Based on OWL-S
Verification Web Services Composition Based on OWL-S
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International Symposium on Knowledge Acquisition and Modeling, KAM
作者: Hong Xia Zengzhi Li State key Laboratory of Networking and Switch Technology Beijing University of Posts and Telecommunications Beijing China Institute of Computer System Architecture and Network Xi''an Jiaotong University Xi'an Shaanxi China
In order to ensure the correctness and reliability of Web services composition based on OWL-S, verify the interaction protocol of Web services. It is provided that three lay architecture. Composition service based on ... 详细信息
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Efficient Physical Design Methodology for Reducing Test Power Dissipation of Scan-Based Designs
Efficient Physical Design Methodology for Reducing Test Powe...
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International Conference on Networking, architecture, and Storage (NAS)
作者: Jun Xu Xiangku Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing China
Scan-based test methodology is used to resolve the sequential-test problem but suffers from high power dissipation. In this paper, we propose a scheme to prevent transitions of scan chain from reflecting into the circ... 详细信息
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Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan
Flip-Flop Selection for Transition Test Pattern Reduction Us...
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Pacific Rim International Symposium on Dependable Computing
作者: Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Enhanced scan delay testing approach can achieve high transition delay fault coverage by a small size of test pattern set but with significant hardware overhead. Although the implementation cost of launch on capture (... 详细信息
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A Low-Complexity Synchronization Based Cache Coherence Solution for Many Cores
A Low-Complexity Synchronization Based Cache Coherence Solut...
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International Conference on computer and Information Technology (CIT)
作者: Wei Lin DongRui Fan He Huang Nan Yuan XiaoChun Ye Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
computer architectures make a dramatic turn away from improving single-processor performance towards improved parallel performance through integrating many cores in one chip. However, providing directory based coheren... 详细信息
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Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy
Variation-Aware Scheduling for Chip Multiprocessors with Thr...
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Pacific Rim International Symposium on Dependable Computing
作者: Jianbo Dong Lei Zhang Yinhe Han Guihai Yan Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Thread-level redundancy in Chip Multiprocessors(TLR-CMP) is efficient for soft error tolerance. Process variation causes core-to-core (C2C) performance asymmetry across a chip, which should be taken into consideration... 详细信息
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Design of New Hash Mapping Functions
Design of New Hash Mapping Functions
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International Conference on computer and Information Technology (CIT)
作者: Fenglong Song Zhiyong Liu Dongrui Fan Junchao Zhang Lei Yu Nan Yuan Wei Lin Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Conflict can decrease performance of computer severely, such as bank conflicts reduce bandwidth of interleave multibank memory systems and conflict misses reduce effective on-chip capacity, and this incurs much confli... 详细信息
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Scaling the Performance of Tiled Processor architectures with On-Chip-Network Topology
Scaling the Performance of Tiled Processor Architectures wit...
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The Second International Joint Conference on Computational Science and Optimization(CSO 2009)(2009 国际计算科学与优化会议)
作者: Yongqing Ren Hong An Ming Cong Guang Xu Li Wang Department of Computer Science and Technology University of Science and Technology of China Hefei 230026 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100080 China
The trend in wire delays due to resistance is becoming a significant problem for microprocessor designers, forcing radically new tiled microprocessor architecture designs. This type of architecture will necessarily in... 详细信息
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Accelerate Cache Simulation with Generic GPU
Accelerate Cache Simulation with Generic GPU
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International Conference on computer and Information Technology (CIT)
作者: Wan Han Gao Xiaopeng Wang Zhiqiang State Key Laboratory of Virtual Reality Technology and System School of Computer Science and Engineering Beihang University Beijing China
Trace-driven cache simulation is the most widely used method to evaluate different cache structures. Several techniques have been proposed to reduce the simulation time of sequential trace-driven simulation. An obviou... 详细信息
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Study on Fine-Grained Synchronization in Many-Core architecture
Study on Fine-Grained Synchronization in Many-Core Architect...
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ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (SNPD)
作者: Lei Yu Zhiyong Liu Dongrui Fan Fenglong Song Junchao Zhang Nan Yuan Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
The synchronization between threads has serious impact on the performance of many-core architecture. When communication is frequent, coarse-grained synchronization brings significant overhead. Thus, coarse-grained syn... 详细信息
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Evaluation Method of Synchronization for Shared-Memory On-Chip Many-Core Processor
Evaluation Method of Synchronization for Shared-Memory On-Ch...
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International Symposium on Parallel and Distributed Processing with Applications, ISPA
作者: Fenglong Song Zhiyong Liu Dongrui Fan He Huang Nan Yuan Lei Yu Junchao Zhang Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
On-chip many core architecture is an emerging and promising computation platform. High speed on-chip communication and abundant chipped resources are two outstanding advantages of this architecture, which provide an o... 详细信息
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