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检索条件"机构=State Key Laboratory of Computer System and Architecture"

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Verification Web Services Composition Based on OWL-S

Verification Web Services Composition Based on OWL-S

引用

International Symposium on Knowledge Acquisition and Modeling, KAM

作者： Hong Xia Zengzhi Li State key Laboratory of Networking and Switch Technology Beijing University of Posts and Telecommunications Beijing China Institute of Computer System Architecture and Network Xi''an Jiaotong University Xi'an Shaanxi China

In order to ensure the correctness and reliability of Web services composition based on OWL-S, verify the interaction protocol of Web services. It is provided that three lay architecture. Composition service based on OWL-S, GA model is the middle model and the Promela model is the verification model, SPIN as a model validator. The OWL-S composition Web services transform a top-down conversation protocol process into a GA model, use WAST tool into Promela model, the SPIN tool analysis and verification structure and performance of composition services. This method is flexibility and scalability which provide a solution for Web services composition model verification.

关键词： Web services XML Protocols state-space methods Scalability Service oriented architecture computer architecture Switches Automata Asynchronous communication

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Online Computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures

Online Computing and Predicting Architectural Vulnerability ...

引用

Pacific Rim International Symposium on Dependable Computing

作者： Songjun Pan Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Soft Errors have emerged as a key challenge to microprocessor design. Traditional soft error tolerance techniques (such as redundant multithreading and instruction duplication) can achieve high fault coverage but at the cost of significant performance degradation. Prior research reports that soft errors can be masked at the architecture level, and the degree of such masking, named as architecture vulnerability factor (AVF), can vary significantly across workloads and individual structures, hence strict redundant execution may not be necessary for soft error tolerance. In this work, we exploit the AVF varying feature to adaptively tune reliability and performance. We present an infrastructure to online compute and predict AVF for three microprocessor structures (IQ, ROB, and LSQ), guiding when the protection scheme should be activated to improve reliability. Experimental results show that our method can efficiently compute the AVF for different structures independent of hardware configurations. The average differences between our method and a prior offline AVF computing method are 0.10, 0.01, and 0.039 for IQ, ROB, and LSQ, respectively.

关键词： Microprocessors Protection computer architecture Multithreading Degradation computer errors Hardware Microarchitecture Material storage Error correction codes

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Efficient Physical Design Methodology for Reducing Test Power Dissipation of Scan-Based Designs

Efficient Physical Design Methodology for Reducing Test Powe...

引用

International Conference on Networking, architecture, and Storage (NAS)

作者： Jun Xu Xiangku Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing China

Scan-based test methodology is used to resolve the sequential-test problem but suffers from high power dissipation. In this paper, we propose a scheme to prevent transitions of scan chain from reflecting into the circuit line. It not only can save 23% power consumption without performance loss, but also can be easily implemented with popular industrial design tools.

关键词： Design methodology Power dissipation Circuit testing Automatic test pattern generation Sequential analysis Registers computer architecture system testing Logic Controllability

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Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan

Flip-Flop Selection for Transition Test Pattern Reduction Us...

引用

Pacific Rim International Symposium on Dependable Computing

作者： Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Enhanced scan delay testing approach can achieve high transition delay fault coverage by a small size of test pattern set but with significant hardware overhead. Although the implementation cost of launch on capture (LOC) approach is relatively low, the generated pattern set for testing delay faults is typically very large. In this paper, we present a novel flip-flop selection method to combine the respective advantages of the two approaches, by replacing a small number of selected regular scan cells with enhanced scan cells, thus to reduce the overall volume of transition delay test patterns effectively. Moreover, higher fault coverage can also be obtained by this approach compared to the standard LOC approach. Experimental results on larger ISCAS-89 and ITC-99 benchmark circuits using a commercial test generation tool show that the volume of test patterns can be reduced by over 70% and the transition delay fault coverage can be improved by up to 8.7%.

关键词： Flip-flops Delay Circuit testing Lab-on-a-chip Circuit faults Test pattern generators system testing Hardware Costs Timing

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A Low-Complexity Synchronization Based Cache Coherence Solution for Many Cores

A Low-Complexity Synchronization Based Cache Coherence Solut...

引用

International Conference on computer and Information Technology (CIT)

作者： Wei Lin DongRui Fan He Huang Nan Yuan XiaoChun Ye Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

computer architectures make a dramatic turn away from improving single-processor performance towards improved parallel performance through integrating many cores in one chip. However, providing directory based coherence protocols for these platforms is too complex and expensive. As a substitute, we propose a synchronization based cache coherence solution, which uses different cache policies according to three flexible software guided scopes (exclusion, producer and consumer scopes) to solve the data-race and coherence problem. Furthermore, this protocol implements word dirty bits (only one bit per word is needed in each L1 cache line) and a special hardware synchronization manager (HSM) to support multi-writer, the write-validate policy and to eliminate the remote un-cache spinning at the ldquoflagrdquo. We evaluate Godson-T, a platform supporting this protocol, against an idealized interleaved dual tag directory based protocol on the Splash2 and two bioinformatics benchmarks. The performance of the synch-based protocol is degraded only at 3.2% on average, but the real chip area is reduced at 32% even if the overhead of HSM is included.

关键词： Protocols computer architecture Hardware Concurrent computing Costs Network-on-a-chip Coherence Tiles Information technology Helium

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Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy

Variation-Aware Scheduling for Chip Multiprocessors with Thr...

引用

Pacific Rim International Symposium on Dependable Computing

作者： Jianbo Dong Lei Zhang Yinhe Han Guihai Yan Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Thread-level redundancy in Chip Multiprocessors(TLR-CMP) is efficient for soft error tolerance. Process variation causes core-to-core (C2C) performance asymmetry across a chip, which should be taken into consideration for application scheduling. In this paper, two types of variations beyond C2C are introduced, i.e., inter-pair and intra-pair variation in TLR-CMP. Intra-pair performance asymmetry can affect the performance of applications differently. Based on the above observation, we firstly formalize the variation aware scheduling in TLR-CMP as a 0-1 programming problem,to maximize the system weighted throughput. An efficient scheduling algorithm, named IntraVarF&AppSen, is then proposed to tackle this problem, which can be proved to be optimal when the number of applications to be scheduled is equal to the number of core pairs. Simulation on a 64-core CMP shows 2.8%-4% improvement in weighted throughput when compared to prior VarF&AppIPC algorithm.

关键词： Yarn Job shop scheduling Redundancy Throughput Scheduling algorithm Cathode ray tubes computer architecture Error analysis Transistors Multiprocessing systems

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Design of New Hash Mapping Functions

Design of New Hash Mapping Functions

引用

International Conference on computer and Information Technology (CIT)

作者： Fenglong Song Zhiyong Liu Dongrui Fan Junchao Zhang Lei Yu Nan Yuan Wei Lin Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Conflict can decrease performance of computer severely, such as bank conflicts reduce bandwidth of interleave multibank memory systems and conflict misses reduce effective on-chip capacity, and this incurs much conflict miss further. Conflicts can be avoided by a suitable address mapping scheme which maps the most frequently occurring patterns conflict-free. In this paper, we present a new XOR-based mapping scheme, called XORM, which focuses on multi-bank shared cache of on-chip many-core architecture. The XORM mapping scheme can map arbitrary bits of address to set indices and compute each set index bit as XOR of a transpositional subset of the bits in the address. Then, we analyze necessary characteristics of an address mapping scheme to avoid conflict in many-core architecture. Next, we give a case study to design optimal hash functions based on XORM scheme for skewed-associative cache. Finally, we introduce another case study, in which we illustrate how to design an XORM mapping scheme with lower implementation cost, complexity and computing latency in shared cache of chipped many-core architecture. The evaluated results show the effectiveness of XORM mapping scheme.

关键词： computer architecture Delay Bandwidth Costs Information technology Laboratories system-on-a-chip Hardware High performance computing Polynomials

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Scaling the Performance of Tiled Processor architectures with On-Chip-Network Topology

Scaling the Performance of Tiled Processor Architectures wit...

引用

The Second International Joint Conference on Computational Science and Optimization(CSO 2009)(2009 国际计算科学与优化会议)

作者： Yongqing Ren Hong An Ming Cong Guang Xu Li Wang Department of Computer Science and Technology University of Science and Technology of China Hefei 230026 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100080 China

The trend in wire delays due to resistance is becoming a significant problem for microprocessor designers, forcing radically new tiled microprocessor architecture designs. This type of architecture will necessarily incorporate on-chip networks topology. This paper examines a few of the possible on-chip network topology in the context of tiled processor architectures. Firstly, by investigating some proposed tiled processor architecture, we observe that the on-chip network interconnecting is the critical design point in the architectures. After that, we discuss the candidate topologies of on-chip network topology that satisfy these properties. Finally, a detailed experimental evaluation of these networks topology is presented to highlight the scalability and performance of these tiled processor architectures. Results show that we can achieve performance improvement by modifying basic mesh appropriately according to the granularity of the tile within technology restrictions.

关键词： Tiles Network topology Wire Network-on-a-chip Microprocessors Delay Switches computer architecture Process design Registers

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Accelerate Cache Simulation with Generic GPU

Accelerate Cache Simulation with Generic GPU

引用

International Conference on computer and Information Technology (CIT)

作者： Wan Han Gao Xiaopeng Wang Zhiqiang State Key Laboratory of Virtual Reality Technology and System School of Computer Science and Engineering Beihang University Beijing China

Trace-driven cache simulation is the most widely used method to evaluate different cache structures. Several techniques have been proposed to reduce the simulation time of sequential trace-driven simulation. An obvious way to achieve fast parallel simulation is to simulate the individual independent sets of a cache concurrently on different compute resources. We propose improvements to current trace-driven simulation methods to make them faster and more economical. This paper considers the use of generic GPU to accelerate cache simulation which exploits set-partitioning as the main source of parallelism. We develop more efficient parallel simulation techniques by introducing more knowledge into the compute unified device architecture (CUDA) on the GPU. Our experimental result shows that the new algorithm can produce performance results for a number of set-associative caches in just a single simulation run and still produce the exact results.

关键词： Acceleration Computational modeling Concurrent computing Graphics Parallel processing computer architecture computer simulation Analytical models Partitioning algorithms Kernel

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Study on Fine-Grained Synchronization in Many-Core architecture

Study on Fine-Grained Synchronization in Many-Core Architect...

引用

ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (SNPD)

作者： Lei Yu Zhiyong Liu Dongrui Fan Fenglong Song Junchao Zhang Nan Yuan Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

The synchronization between threads has serious impact on the performance of many-core architecture. When communication is frequent, coarse-grained synchronization brings significant overhead. Thus, coarse-grained synchronization is not suitable for this situation. However, the overhead of fine-grained synchronization is still small when the communication is frequent. For the many-core architecture which supports fine-grained synchronization with on-chip storage, we propose fine-grained synchronization algorithms for scientific computation application 2-D wavefront and LU decomposition. At first, according to the memory access mode, an efficient method of data allocation is proposed. Then, way of thread partition and synchronization are discussed. Finally, we estimate the two algorithms based on Godson-T many-core architecture. The results of experiments show that the relative speedup is almost linear and the execution time is only 53.2 % of the coarse-grained synchronization. After the global barriers are eliminated, LU decomposition achieved 13.1% performance improvement. Moreover, the experiments prove that the fine-grained mechanism is able to improve the performance of processor and it has a good scalability.

关键词： Frequency synchronization computer architecture Yarn Parallel processing Distributed computing Concurrent computing Delay Programming profession Partitioning algorithms Wire

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