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IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： Zichu Qi Hui Liu Xiangku Li Jun Xu Weiwu Hu Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424450909;9781424450916

For a gigahertz microprocessor with multiple clock domains and a large amount of embedded RAMs (random access memory), generating at-speed testing patterns is becoming very difficult and very time-consuming. This paper presents some novel techniques to improve at-speed testing coverage with low cost. These methods are major concern about preventing X states propagation, which include avoiding capturing X states for registers, sequential bypass of macros, clock control scheme for inter-clock domains and accurate analysis of exception paths in intra-clock domains. Functional patterns are utilized to further improve the efficiency of the at-speed testing. A novel optimal flow is presented by carefully selecting these techniques. By using the flow, 90% transition fault coverage is achieved. In addition, both the number of patterns and the test time of the transition test are decreased by 15%. The total area overhead is about a few hundreds of AND cells and has little timing impact on the critical paths.

关键词： Microprocessors Clocks Test pattern generators system testing Costs Timing Automatic test pattern generation Delay Pattern analysis Laboratories

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Data Management: The Spirit to Pursuit Peak Performance on Many-Core Processor

Data Management: The Spirit to Pursuit Peak Performance on M...

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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Yongbin Zhou Junchao Zhang Shuai Zhang Nan Yuan Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

To date, most of many-core prototypes employ tiled topologies connected through on-chip networks. The throughput and latency of the on-chip networks usually become to the bottleneck to achieve peak performance especially for communication intensive applications. Most of studies are focus on on-chip networks only, such as routing algorithms or router micro-architecture, to improve the above metrics. The salient aspect of our approach is that we provide a data management framework to implement high efficient on-chip traffic based on overall many-core system. The major contributions of this paper include that: (1) providing a novel tiled many-core architecture which supports software controlled on-chip data storage and movement management; (2) identifying that the asynchronous bulk data transfer mechanism is an effective method to tolerant the latency of 2-D mesh on-chip networks. At last, we evaluate the 1-D FFT algorithm on the framework and the performance achieves 47.6 Gflops with 24.8% computation efficiency.

关键词： Network-on-a-chip Delay Prototypes Network topology Throughput Routing system-on-a-chip Communication system traffic control computer architecture Memory

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Detecting and Eliminating Potential Violations of Sequential Consistency for Concurrent C/C++ Programs 09

Detecting and Eliminating Potential Violations of Sequential...

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International Symposium on Code Generation and Optimization (CGO)

作者： Yuelu Duan Xiaobing Feng Lei Wang Chao Zhang Pen-Chung Yew Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Department of Computer Science and Engineering University of Minnesota Twin-Cities Minneapolis USA

ISBN: (纸本)9780769535760

When a concurrent shared-memory program written with a sequential consistency (SC) model is run on a machine implemented with a relaxed consistency (RC) model, it could cause SC violations that are very hard to debug. To avoid such violations, programmers need to provide explicit synchronizations or insert fence instructions. In this paper, we propose a scheme to detect and eliminate potential SC violations by combining Shasha/Snir's conflict graph and delay set theory with existing data race detection techniques. For each execution, we generate a race graph, which contains the improperly synchronized conflict accesses, called race accesses, and race cycles formed with those accesses. As a race cycle would probably lead to a non-sequential-consistent execution, we call it a potential violation of sequential consistency (PVSC) bug. We then compute the race delays of race cycles, and suggest programmers to insert fences into source code to eliminate PVSC bugs. We further convert a race graph into a PC race graph, and improves cycle detection and race delay computation to O(n 2 ), where n is the number of race access instructions. We evaluate our approach with the SPLASH-2 benchmarks, two large real-world applications (MySQL and Apache), and several multi-threaded Cilk programs. The results show that (1) the proposed approach could effec-tively detect PVSC bugs in real-world applications with good scalability; (2) it retains most of the performance of the concurrent program after inserting required fence instructions, with less than 6.3% performance loss; and (3) the additional cost of our approach over traditional race detection techniques is quite low, with 3.3% on average.

关键词： Programming profession Delay Set theory computer bugs Performance loss Chaos computer science Laboratories Concurrent computing computer architecture

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Set of model reduction rules and algorithms for web services composition under orchestration pattern

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Hsi-An Chiao Tung Ta Hsueh/Journal of Xi'an Jiaotong University 2009年第6期43卷 20-23+47页

作者： Yang, Huaizhou Li, Zengzhi Institute of Computer Architecture and Networks Xi'an Jiaotong University Xi'an 710049 China State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications Beijing 100876 China

The performance calculation of Web services composition process in large state space is time-consuming, and is difficult to fulfill the real-time performance analysis. Therefore, a process reduction algorithm is presented to accelerate the calculation of system performance. The Web services composition process is modeled using the generalized stochastic Petri net. Through auto-detecting the reductive subnet, some regular structures, such as sequence, choice, concurrent and loop structures, can be eliminated under the precondition of preserving the timing constraints. The sub processes which can be calculated independently are separated. A large scale model can thus be reduced within a certain period. Experimental results with multiform models indicate that the system response time and throughput are obtained rapidly by using the algorithm in the dynamic and adaptive composition process. The algorithm can be applied to online performance analysis of most Web services composition process.

关键词： Stochastic systems

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Mean Shift Based Collaborative Localization with Dynamically Clustering for Wireless Sensor Networks

Mean Shift Based Collaborative Localization with Dynamically...

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WRI International Conference on Communications and Mobile Computing, CMC

作者： Quan Zhou Xiaowei Li Yongjun Xu Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China Institute of Computing Technology Laboratory of Sensor Networks Chinese Academy and Sciences Beijing China

Mean shift is a nonparametric method to estimate the density gradient, which iteratively computes the mean of observations and shifts to the centroid until reach a predefined end condition. This paper proposes a mean shift based scheme for localization and tracking in wireless sensor *** shift is a generalized framework, and range-free centroid and range-based W-Centrod are both the special cases of this generalized framework. A dynamically clustering protocol is proposed to support the generalized framework. Analysis and simulation results show that the communication overhead and jitter are reduced to 1/3 of traditional algorithms. The positioning accuracy of proposed algorithm with optimal weight increases 28% and 11% in comparison to Centroid and W-Centroid.

关键词： Wireless sensor networks computer networks Clustering algorithms Laboratories Protocols Equations Mobile communication Mobile computing International collaboration computer architecture

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Smallest Enclosing Circle Based Localization Approach for Wireless Sensor Networks

Smallest Enclosing Circle Based Localization Approach for Wi...

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WRI International Conference on Communications and Mobile Computing, CMC

作者： Quan Zhou Xiaowei Li Yongjun Xu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Laboratory of Sensor Networks Institute of Computing Technology Chinese Academy and Sciences Beijing China

A novel range-free localization approach, smallest enclosing Circle based Localization (SECL), has been proposed. This approach uses the center of smallest enclosing circle of neighboring anchor nodes to estimate the position of target. Comparing to centroid, SECL considers the geometrical coverage of anchors rather than the mass center of them. Consequently, SECL is robust to imperfect topology, especially when the topology of anchors is depolyed unevenly. Simulation results show that SECL outperforms Centroid by an average of 10%, and even better when the topology is not uniform.

关键词： Wireless sensor networks Network topology computer networks Laboratories Robustness Computational modeling Equations Hardware Mobile communication Mobile computing

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Using GPU to Accelerate Cache Simulation

Using GPU to Accelerate Cache Simulation

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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Wan Han Gao Xiaopeng Wang Zhiqiang Li Yi State Key Laboratory of Virtual Reality Technology and System School of Computer Science and Engineering Beijing Aeronautics and Astronautics University Beijing China

Caches play a major role in the performance of high speed computer systems. Trace driven simulator is the most widely used method to evaluate cache architectures. However, as the cache design moves to more complicated architectures, along with the size of the trace is becoming larger and larger. Traditional simulation methods are no longer practical due to their long simulation cycles. Several techniques have been proposed to reduce the simulation time of sequential trace driven simulation. This paper considers the use of generic GPU to accelerate cache simulation which exploits set partitioning as the main source of parallelism. We develop more efficient parallel simulation techniques by introducing more knowledge into the Compute Unified Device architecture (CUDA) on the GPU. Our experimental result shows that the new algorithm gains 2.76 times performance improvement compared to traditional CPU based sequential algorithm.

关键词： Acceleration Computational modeling computer architecture Analytical models Concurrent computing computer simulation High performance computing Parallel processing Parallel algorithms Distributed processing

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TACS: A Transparent Application Bandwidth Management system

TACS: A Transparent Application Bandwidth Management System

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International Conference on computer and Information Technology (CIT)

作者： Xianqin Chen Xiang Long Xiaopeng Gao Junjie Ma State Key Laboratory of Virtual Reality Technology and System School of Computer Science and Technology Beijing Aeronautics and Astronautics University Beijing China

With the rapid advance of computer and network technology, more and more applications are deployed in the customer-side network. These applications require different quality of service (QoS), but have to share a few bandwidth limited Internet connections. Owing to the IP network's best-effort delivery mechanism, the QoS requirements are hard to be satisfied. There have been plenty of QoS solutions in research and industry areas, however, few of them are easy to understand or to deploy. Therefore, we provide a solution, based on a simple and clear model, has the ability of transparently deployed at the inner side of customer's gateway device and controlled in the application-oriented way. We also introduce a straightforward QoS policy definition language to allow user to create QoS rules for various applications. We conduct the evaluation of our prototype system running upon mid-end industrial personal computer under both the lab test-bed and the practical network. In the lab test, our system achieves 200Mbps throughput, in the practical field test, our system successfully manages a 100Mbps Internet link for over 3000 active users.

关键词： Bandwidth Quality of service Application software system testing computer networks Web and internet services Prototypes computer industry Electrical equipment industry Microcomputers

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A stochastic method for controlling the scaling parameters of Cauchy mutation in fast evolutionary programming

A stochastic method for controlling the scaling parameters o...

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Congress on Evolutionary Computation

作者： Yunji Chen Ke Tang Tianshi Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Nature Inspired Computation and Applications Laboratory Department of Computer Science and Technology University of Science and Technology of China Hefei Anhui China

The fast evolutionary programming (FEP) introduced the Cauchy distribution into its mutation operator, thus the performances of EP were promoted significantly on a number of benchmark problems. However, the scaling parameter of the Cauchy mutation is invariable, which has become an obstacle for FEP to reach better performance. This paper proposes and analyzes a new stochastic method for controlling the variable scaling parameters of Cauchy mutation. This stochastic method collects information from a group of individuals randomly selected from the population. Empirical evidence validates our method to be very helpful in promoting the performance of FEP.

关键词： Stochastic processes Genetic mutations Genetic programming Laboratories Random variables Gaussian distribution Control systems Stochastic systems computer architecture computer applications

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Optimizing inter-domain communication

Optimizing inter-domain communication

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15th International Conference on Parallel and Distributed systems, ICPADS '09

作者： Zang, Hongyong Sun, Yuzhong Gu, Kuiyan Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University of Chinese Academy of Sciences Beijing 100049 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Dongxin Geology Research Institute of Shengli Oilfield Sinopec Dongying Shandong 257094 China

ISBN: (纸本)9780769539003

Virtual machine technology has played an important role in data center. Distributed services deployed in multiple virtual machines, may reside on one physical machine. This situation requires an efficient inter-domain communication channel with transparency and security principles ensured. Although current inter-domain mechanism has gained a much better performance compared to traditional inter-domain path offered by hypervisor, shared data channel size limitation and additional copy are still two restrains against a higher performance efficiency. In this paper, we give an analysis on these limitations, overcome these shortcomings, and achieve a higher efficient inter-domain communication channel. By applying virtual address protection mechanism during channel bootstrap, we enlarge the maximum size of shared data channel. By pointing network packet structure to the buffer in the shared data channel, we avoid an extra data copy on the receiver VM side. In our evaluation using a number of standard benchmarks, we have reduced the latency by nearly 40%, increased the throughput by approximately 45% and cut down more than 3500 CPU cycles per packet. © 2009 IEEE.

关键词： Virtual machine

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