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Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor systems of Cluster Platforms

Journal of computer Science & Technology 2014年第1期29卷 21-37页

作者：吕方崔慧敏王蕾刘磊武成岗冯晓兵游本中 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences CCF ACM IEEE Department of Computer Science and Engineering University of Minnesota at Twin Cities Institute of Information Science Academia Sinica

Efficiency of batch processing is becoming increasingly important for many modern commercial service centers, e.g., clusters and cloud computing datacenters. However, periodical resource contentions have become the major performance obstacles for concurrently running applications on mainstream CMP servers. I/O contention is such a kind of obstacle, which may impede both the co-running performance of batch jobs and the system throughput seriously. In this paper, a dynamic I/O-aware scheduling algorithm is proposed to lower the impacts of I/O contention and to enhance the co-running performance in batch processing. We set up our environment on an 8-socket, 64-core server in Dawning Linux Cluster. Fifteen workloads ranging from 8 jobs to 256 jobs are evaluated. Our experimental results show significant improvements on the throughputs of the workloads, which range from 7% to 431%. Meanwhile, noticeable improvements on the slowdown of workloads and the average runtime for each job can be achieved. These results show that a well-tuned dynamic I/O-aware scheduler is beneficial for batch-mode services. It can also enhance the resource utilization via throughput improvement on modern service platforms.

关键词： chip multiprocessor batch processing co-running I/0 contention scheduling

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K-Nearest Neighbor Algorithm Implementation on FPGA Using High Level Synthesis 13

K-Nearest Neighbor Algorithm Implementation on FPGA Using Hi...

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2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Zhe-Hao Li Ji-Fang Jin Xue-Gong Zhou Zhi-Hua Feng State Key Laboratory of ASIC & System Fudan University Beijing Institute of Computer Technology and Application

ISBN: (纸本)9781467397209

The K-Nearest Neighbor(K-NN) algorithm is one of the most common classification algorithms and widely used in pattern recognition and data mining. K-NN hardware acceleration is necessary for applications with massive high-dimensional data. High level synthesis(HLS) is an increasingly adopted technique in digital circuit design, which can help to raise the abstraction levels. In this paper, we exploit the parallelism and pipelining opportunities and apply the memory-mapped AXI4-Master Interface to implement K-NN on an FPGA using HLS. The evaluation result shows that our HLS-based solution is 35.1x faster than a general purpose processor(GPP) based implementation, and comparable to hardware description language(HDL) based implementations, while our HLS-based solution largely reduces the development complexity and cost.

关键词： K-Nearest Neighbor Algorithm Implementation on FPGA Using High Level Synthesis HLS

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STEED: An analytical database system for TrEE-structured data 43

STEED: An analytical database system for TrEE-structured dat...

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43rd International Conference on Very Large Data Bases, VLDB 2017

作者： Wang, Zhiyi Zhou, Dongyan Chen, Shimin State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

Tree-structured data formats, such as JSON and Protocol Buffers, are capable of expressing sophisticated data types, including nested, repeated, and missing values. While such expressing power contributes to their popularity in real-world applications, it presents a significant challenge for systems supporting tree-structured data. Existing systems have focused on general-purpose solutions either extending RDBMSs or designing native systems. However, the general-purpose approach often results in sophisticated data structures and algorithms, which may not reflect and optimize for the actual structure patterns in the real world. In this demonstration, we showcase Steed, an analytical database system for tree-structured data. We use the insights gained by analyzing representative real-world tree structured data as guidelines in the design of Steed. Steed learns and extracts a schema tree for a data set and uses the schema tree to reduce the storage space and improve the efficiency of data field accesses. We observe that sub-structures in real world data are often simple, while the treestructured data types can support very sophisticated structures. We optimize the storage structure, the column assembling algorithm, and the in-memory layout for the simple sub-structures (a.k.a. simple paths). Compared to representative state-of-the-art systems (i.e. PostgreSQL/JSON, MongoDB, and Hive+Parquet), Steed achieves orders of magnitude better performance for data analysis queries. © 2017 VLDB Endowment.

关键词： Database systems

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SOOP: Efficient Distributed Graph Computation Supporting Second-Order Random Walks

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Journal of computer Science & Technology 2021年第5期36卷 985-1001页

作者： Songjie Niu Dongyan Zhou State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China Bytedance Technology Beijing 100086China

The second-order random walk has recently been shown to effectively improve the accuracy in graph analysis *** work mainly focuses on centralized second-order random walk(SOW)*** algorithms rely on edge-to-edge transition probabilities to generate next random ***,it is prohibitively costly to store all the probabilities for large-scale graphs,and restricting the number of probabilities to consider can negatively impact the accuracy of graph analysis *** this paper,we propose and study an alternative approach,SOOP(second-order random walks with on-demand probability computation),that avoids the space overhead by computing the edge-to-edge transition probabilities on demand during the random ***,the same probabilities may be computed multiple times when the same edge appears multiple times in SOW,incurring extra cost for redundant computation and *** propose two optimization techniques that reduce the complexity of computing edge-to-edge transition probabilities to generate next random steps,and reduce the cost of communicating out-neighbors for the probability computation,*** experiments on real-world and synthetic graphs show that SOOP achieves orders of magnitude better performance than baseline precompute solutions,and it can efficiently computes SOW algorithms on billion-scale graphs.

关键词： second-order random walk(SOW) Node2Vec second-order PageRank distributed graph computation SOOP(second-order random walks with on-demand probability computation)

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Co-optimization of Dynamic/Static Test PoWer in Scan Test

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电子学报(英文版) 2009年第1期18卷 54-58页

作者： WANG Wei HAN Yinhe LI Xiaowei FANG Fang School of Computer and Information Hefei University of Technology Hefei 230009 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China School of Management Hefei University of Technology Hefei 230009 China

Low-power design has become a challenge of test. We propose an effective low-power scan architecture named PowerSluice to minimize power consumption during scan test, which is based on scan chain modifications. On one hand, a kind of blocking logic is inserted into the scan chain to reduce the dynamic power and two kinds of controlling units are also inserted to decrease the leakage power during the shift cycle. On the other hand, using genetic algorithm, the exact values of control signals are found out to control the process. Experiments results indicate that this architecture can effectually reduce power during scan test with probably minimum area cost.

关键词：低功耗设计扫描测试静态测试动态优化合作控制单元电力消耗动态功耗

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Wear rate leveling: Lifetime enhancement of PRAM with endurance variation

Wear rate leveling: Lifetime enhancement of PRAM with endura...

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作者： Dong, Jianbo Zhang, Lei Han, Yinhe Wang, Ying Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450306362

The limited write endurance of phase change random access memory (PRAM) is one of the major obstacles for PRAM-based main memory. Wear leveling techniques were proposed to extend its lifetime by balancing writes traffic. Another important concern that need to be considered is endurance variation in PRAM chips. When different PRAM cells have distinct endurance, balanced writes will result in lifetime degradation due to the weakest cells. Instead of balancing writes traffic, in this paper we propose wear rate leveling (WRL), a variant of wear leveling, to balance wear rates (i.e., writes traffic/edudrance) of cells across the PRAM chip. After investigating writing behavior of applications and endurance variation, we propose an architecture-level WRL mechanism. Moreover, there is an important tradeoff between endurance improvement and swapping data volume. To co-optimize endurance and swapping, a novel algorithm, Max Hyper-weight Rematching, is proposed to maximize PRAM lifetime and minimize performance degradation. Experimental results show 19x endurance improvement to prior Wear Leveling © 2011 ACM.

关键词： Phase change memory

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Flex memory: Exploiting and managing abundant off-chip optical bandwidth

Flex memory: Exploiting and managing abundant off-chip optic...

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作者： Wang, Ying Zhang, Lei Han, Yinhe Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783981080179

The emerging nanophotonic technology can avoid the limitation of I/O pin count, and provide abundant memory bandwidth. However, current DRAM organization has mainly been optimized for a higher storage capacity and package pin utilization. The resulted data fetching mechanism is quite inefficient in performance and energy saving, and cannot effectively utilize the abundant optical bandwidth in off-chip communication. This paper inspects the opportunity brought by optical communication, and revisits the DRAM memory architecture considering the technology trend towards multiprocessors. In our FlexMemory design, super-line prefetching is proposed to boost system performance and promote energy efficiency, which leverages the abundant photonic bandwidth to enlarge the effective data fetch size per memory cycle. To further preserve locality and maintain service parallelism for different workloads, page folding technique is employed to achieve adaptive data mapping in photonics-connected DRAM chips via optical wavelengths allocation. By combining both techniques, surplus off-chip bandwidth can be utilized and effectively managed adapting to the workloads intensity. Experimental results show that our FlexMemory achieves considerable improvements in performance and energy efficiency. © 2011 EDAA.

关键词： Dynamic random access storage

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Hyper-Distributed Hyper-Parallel Self-Organizing Dynamic Scheduling Based on Solitary Wave

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Journal of computer Science & Technology 2001年第5期16卷 434-442页

作者：帅典勋顾静顾慧平邓志东 Department of Computer Science East China University of Science and Technology Shanghai P.R. China State Key Laboratory of Intelligence Technology and System Tsinghua University Beijing P.R. China

This paper presents a new soliton approach to hyper-distributed hyper-parallel self-organizing dynamic scheduling for task allocations among rational autonomous agents in a multi-agent system (MAS). This approach can overcome many drawbacks of other mechanisms currently used for coalition formation and cooperation in MAS. The thorny problems, such as overabundant bid, social behaviors, colony intelligence, variable neighbors, and interdepen-dency, can easily be treated by using the proposed approach, whereas they are very difficult for other conventional approaches. The simulation on a distributed transport scheduling sys-tem shows the soliton approach featured by hyper-parallelism, effectiveness, openness, dynamic alignment and adaption.

关键词： soliton distributed artificial intelligence multi-agent system hyper-distributed hyper-parallel problem-solving dynamic task allocation

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An Efficient Network-on-Chip Router for Dataflow architecture

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Journal of computer Science & Technology 2017年第1期32卷 11-25页

作者： Xiao-Wei Shen Xiao-Chun Ye Xu Tan Da Wang Lunkai Zhang Wen-Ming Li Zhi-Min Zhang Dong-Rui Fan Ning-Hui Sun State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing 100049 China Department of Computer Science The University of Chicago IL 60637 U.S.A.

Dataflow architecture has shown its advantages in many high-performance computing cases. In dataflow computing, a large amount of data are frequently transferred among processing elements through the network-on-chip （NoC）. Thus the router design has a significant impact on the performance of dataflow architecture. Common routers are designed for control-flow multi-core architecture and we find they are not suitable for dataflow architecture. In this work, we analyze and extract the features of data transfers in NoCs of dataflow architecture： multiple destinations, high injection rate, and performance sensitive to delay. Based on the three features, we propose a novel and efficient NoC router for dataflow architecture. The proposed router supports multi-destination; thus it can transfer data with multiple destinations in a single transfer. Moreover, the router adopts output buffer to maximize throughput and adopts non-flit packets to minimize transfer delay. Experimental results show that the proposed router can improve the performance of dataflow architecture by 3.6x over a state-of-the-art router.

关键词： multi-destination router network-on-chip dataflow architecture high-performance computing

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Functionalised B-Cu@F-Ag@Au trimetallic nanomaterials with long term stability for rapid and highly sensitive in situ SERS detection of furfural in transformer oil

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High Voltage 2023年第2期8卷 293-304页

作者： Yu Lei Changding Wang Weiping Kong Mingliang Wang Xinyuan Zhang Abdolmaleki Nima Caisheng Wang Weigen Chen Fu Wan School of Electrical Engineering Chongqing UniversityChongqingChina State Key Laboratory of Power Transmission Equipment and System Security and New Technology Chongqing UniversityChongqingChina Electrical and Computer Engineering Wayne State UniversityWayneNebraskaUSA

The surface-enhanced Raman scattering(SERS)substrates enable a highly sensitive detection of furfural in the transformer ***,detection substrates with long-term stability are still extremely *** this work,we anchored the thiol-containing coupling agents 2,5-dimercapto-1,3,4-thiadiazole(DMTD)and 1,4-benzenedithiol(BDT)on the surface of bubble copper(B-Cu)and flower-like silver nanoparticles(FAg),*** three-dimensional SERS detection substrates with long-term stability by using a combination of chemical reduction and self-assembly methods were *** substrate has a minimum detection limit of 10^(−9) M for rhodamine B in oil with an enhancement factor of up to 2.23×10^(7).Importantly,the three-crystal BCu@F-Ag_(1)@Au_(5) substrate was used for the detection of furfural in the transformer oil with a detection limit of 2 mg/L and a relative standard deviation value of 2.46%.After 60 days of a simulated operation,the detection signal of furfural in the transformer oil samples at 75℃ and still reached the initial value of 77.53%,indicating that the substrate has a good long-term *** triple frame structured SERS detection platform shows great potential in tracking furfural in the aging transformer oil mixing systems.

关键词： stability. stability SERS

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