We report the measured group delay dispersion of Yb:YAB and compared with that provided by the crystal supplier, over the wavelength from 1000nm to 1080nm. The data are useful for the optimization of the dispersion co...
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ISBN:
(纸本)1424411742
We report the measured group delay dispersion of Yb:YAB and compared with that provided by the crystal supplier, over the wavelength from 1000nm to 1080nm. The data are useful for the optimization of the dispersion compensation for shorter pulse generation in Yb:YAB lasers.
E-CNF is hybrid of Boolean formula and mathematic formula. SAT-based arithmetic circuit bug-hunting method translates the verification problem into E-CNF, and solves E-CNF through E-SAT solver, E-SAT solver is an exte...
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E-CNF is hybrid of Boolean formula and mathematic formula. SAT-based arithmetic circuit bug-hunting method translates the verification problem into E-CNF, and solves E-CNF through E-SAT solver, E-SAT solver is an extension of complete SAT solver, with tag clause technique. Experiments show that SAT-based arithmetic bug-hunting method is powerful in finding bugs in arithmetic circuits.
2-D projective moment invariants were firstly proposed by Suk and Flusser in [12]. We point out here that there is a useless projective moment invariant which is equivalent to zero in their paper. 3-D projective momen...
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2-D projective moment invariants were firstly proposed by Suk and Flusser in [12]. We point out here that there is a useless projective moment invariant which is equivalent to zero in their paper. 3-D projective moment invariants are generated theoretically by investigating the property of signed volume of a tetrahedron. The main part is the selection of permutation invariant cores for multiple integrals to generate independent and nonzero 3-D projective moment invariants. We give the conclusion that projective moment invariants don't exist strictly speaking because of their convergence problem.
The bandwidth becomes the major bottleneck of the performance improvement for modern microprocessors. A cache adaptive write allocate policy that improves the bandwidth of microprocessor significantly is proposed by i...
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The bandwidth becomes the major bottleneck of the performance improvement for modern microprocessors. A cache adaptive write allocate policy that improves the bandwidth of microprocessor significantly is proposed by investigating cache store misses. The cache adaptive write allocate policy collects fully modified blocks in miss queue. Fully modified blocks are written to lower level memory based on non-write allocate policy which can switch to write allocate policy adaptively. Compared with other cache store miss policies, the cache adaptive write allocate policy avoids unnecessary memory traffic, reduces cache pollution and decreases load and store queue full rate without increasing hardware overhead. Experiment results indicate that on average 62.6% memory bandwidth in STREAM benchmarks is improved by utilizing the cache adaptive write allocate policy. The performance of SPEC CPU 2000 benchmarks is also improved efficiently. The average IPC speedup is 5.9%.
The proposed method is focused on synthesis-based static circuits, and a power modeling library is developed for modeling processors by means of parametric RTL and physical annotation, and all kinds of processor modul...
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The proposed method is focused on synthesis-based static circuits, and a power modeling library is developed for modeling processors by means of parametric RTL and physical annotation, and all kinds of processor modules are mapped into combinations of basic components. Those models are linked to an architectural simulator, running benchmarks to get power results. The power analysis of benchmark platforms proves to be effective and highly correlated, with an average 10% error and little speed penalty compared with the gate-level power analysis.
Now the research of computerarchitecture focuses on how to utilize the energy of CPU to attain high performance as much as possible. Obviously the architecture-level power estimation tool is important. Existing archi...
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Now the research of computerarchitecture focuses on how to utilize the energy of CPU to attain high performance as much as possible. Obviously the architecture-level power estimation tool is important. Existing architecture-level power simulators only focus on full-custom dynamic circuits modeling, but ignores the power modeling of ASIC designs which are mainly composed of static circuits or standard cell libraries. So this paper is concerned with the implementation of a high performance and low power general purpose CPU, the Godson-2 processor, and analyzes the power characteristics of the CPU, and implements an architecture-level power estimation methodology which aims at the Godson-2 processor. This methodology takes the power modeling methodology of CMOS static circuits into account carefully, so it is better for the estimation of current high performance CPU architecture which is designed with ASIC methodology. Compared with the RTL power estimating method, this methodology has high speed and high flexibility and the accuracy is also very good. On the platform of Intel Xeon 2.4 GHz, the speed of this methodology is about 300 K instructions per second, which is 5000 times that of the RTL power estimating method with only little error penalty.
Based on the mixed boundary element method, this paper proposes several techniques for 3D impedance extraction, including an efficient organization and row-column adjustment of the sparse coefficient matrix, and a pre...
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Based on the mixed boundary element method, this paper proposes several techniques for 3D impedance extraction, including an efficient organization and row-column adjustment of the sparse coefficient matrix, and a pre-conditioned iterative equation solver. A fast impedance extractor is formed with these techniques. The proposed method has faster speed than the newly-developed FastImp by MIT, while preserving high accuracy. Numerical experiments on two typical interconnect structures verify the efficiency of this method.
This paper presents a multiparameter moment-matching based model order reduction technique for parameterized interconnect networks via a novel two-directional Arnoldi process. It is referred to as a PIMTAP algorithm, ...
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This paper presents a multiparameter moment-matching based model order reduction technique for parameterized interconnect networks via a novel two-directional Arnoldi process. It is referred to as a PIMTAP algorithm, which stands for Parameterized Interconnect Macromodeling algorithm via a Two-directional Arnoldi Process. PIMTAP inherits the advantages of previous multiparameter moment-matching algorithms and avoids their shortfalls. It is numerically stable and adaptive, and preserves the passivity of parameterized RLC networks.
This paper proposes a random routing algorithm with end-to-end feedback. Random routing has the capability of handling random transmission errors efficiently with high forwarding speed. End-to-end feedback promises th...
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This paper proposes a random routing algorithm with end-to-end feedback. Random routing has the capability of handling random transmission errors efficiently with high forwarding speed. End-to-end feedback promises the correctness of transmission and reduces the power consumption. Experimental results demonstrated that our random routing algorithm has lower latency, lower power consumption, and can provide on-chip communication with high reliability.
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