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Latency critical big data computing in finance

Journal of Finance and Data Science 2015年第1期1卷 33-41页

作者： Tian, Xinhui Han, Rui Wang, Lei Lu, Gang Zhan, Jianfeng State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China

Analytics based on big data computing can benefit today's banking and financial organizations on many aspects, and provide much valuable information for organizations to achieve more intelligent trading, which can help them to gain a great competitive advantage. However, the large scale of data and the critical latency analytics requirement in finance poses a great challenge for current system architecture. In this paper, we first analyze the challenges brought by the financial latency critical big data computing, then propose a discussion on how to handle these challenges from a perspective of multi-level system. We also talk about current researches on low latency in different system levels. The discussions and conclusions in the paper can be useful to the banking and financial organizations with the critical latency requirement of big data analytics. © 2015 China Science Publishing & Media Ltd.

关键词： Big data Financial analytics Latency

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Building algorithmically nonstop fault tolerant MPI programs

Building algorithmically nonstop fault tolerant MPI programs

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18th International Conference on High Performance Computing, HiPC 2011

作者： Wang, Rui Yao, Erlin Chen, Mingyu Tan, Guangming Balaji, Pavan Buntinas, Darius State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Mathematics and Computer Science Argonne National Laboratory United States

ISBN: (纸本)9781457719516

With the growing scale of high-performance computing (HPC) systems, today and more so tomorrow, faults are a norm rather than an exception. HPC applications typically tolerate fail-stop failures under the stop-and-wait scheme, where even if only one processor fails, the whole system has to stop and wait for the recovery of the corrupted data. It is now a more-or-less accepted fact that the stop-and-wait scheme will not scale to the next generation of HPC systems. Inspired by the previous stop-and-wait algorithm-based fault tolerance (ABFT) recovery technique, we propose in this paper a nonstop fault tolerance scheme at the application level and describe its implementation. When failure occurs during the execution of applications, we do not stop to wait for the recovery of the corrupted node;instead, we replace it with the corresponding redundant node and continue the execution. At the end of execution, the correct solution can be recovered algorithmically at a very low cost. In order to implement the scheme, some new fault-tolerant features of the Message Passing Interface (MPI) have been investigated and utilized in the MPICH implementation of MPI. We also describe a case study using High Performance Linpack (HPL) with these new features and evaluate the performance of both our new scheme and ABFT recovery. Experimental results show the advantage of our new scheme over ABFT recovery even in a small scale. © 2011 IEEE.

关键词： Message passing

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TMemCanal: A VM-oblivious dynamic memory optimization scheme for virtual machines in cloud computing

TMemCanal: A VM-oblivious dynamic memory optimization scheme...

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10th IEEE International Conference on computer and Information Technology, CIT-2010, 7th IEEE International Conference on Embedded Software and systems, ICESS-2010, 10th IEEE Int. Conf. Scalable Computing and Communications, ScalCom-2010

作者： Li, Yaqiong Huang, Yongbing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate University Chinese of Academy of Sciences China

ISBN: (纸本)9780769541082

In current virtualized cloud platforms, resource provisioning strategy is still a big challenge. Provisioning will gain low resource utilization based on peak workload, and provisioning based on average work loads will sacrifice the potential revenue of cloud customers because of bad user experiences. VM-based performance isolation also restrains resource flowing on demand. As to memory, this eventually results in under-loaded memory and over-loaded memory in the same data center. This paper proposes a VM-oblivious dynamic memory optimization scheme, TMemCanal, which leverages under-loaded memory in a data center to accommodate the needs of loaded memory dynamically in a transparent fashion. TMemCanal is able to identify the under-loaded memory located in different VMs and reuse it in a way of memory flowing without any modification to their Guest OSs. We implemented TMemCanal through extending Xen hypervisor and evaluated using SpecWeb 2005 and LinkPack Benchmarks. Our evaluation shows that TMemCanal can efficiently save memory up to 50% with an overhead less than 7%. Our case study of server consolidation also shows TMemCanal can promote the performance of memory-intensive services up to 400%. © 2010 IEEE.

关键词： Virtual machine

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Equality detection for linear arithmetic constraints

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Journal of Zhejiang University-Science A(Applied Physics & Engineering) 2009年第12期10卷 1784-1789页

作者： Li LI Kai-duo HE Ming GU Xiao-yu SONG Department of Computer Science and Technology Tsinghua University Beijing 100084 China School of Software Tsinghua University Beijing 100084 China MOE Key Laboratory for Information System Security Beijing 100084 China Department of Electrical and Computer Engineering Portland State University Oregon 97207 USA

Satisfiability modulo theories (SMT) play a key role in verification applications. A crucial SMT problem is to combine separate theory solvers for the union of theories. In previous work, the simplex method is used to determine the solvability of constraint systems and the equalities implied by constraint systems are detected by a multitude of applications of the dual simplex method. We present an effective simplex tableau-based method to identify all implicit equalities such that the simplex method is harnessed to an irreducible minimum. Experimental results show that the method is feasible and effective.

关键词： Model checking Satisfiability modulo theories （SMT） Linear arithmetic

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Reducing Synchronization Cost for Single-Level Store in Mobile systems

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Journal of computer Science & Technology 2016年第4期31卷 836-848页

作者： Yuan-Chao Xu Hu Wan Ke-Ni Qiu Tao Li Wei-Gong Zhang College of Information Engineering Capital Normal University Beijing 100048 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Department of Electrical and Computer Engineering University of Florida Gainesville FL 32611 U.S.A.

Emerging byte-addressable non-volatile memory technologies, such as phase change memory （PCM） and spin- transfer torque RAM （STT-RAM）, offer both the byte-addressability of memory and the durability of storage, thus making it feasible to build single-level store systems. To ensure the consistency of persistent data structures in the presence of power failures or system crashes, it requires flushing cache lines to persistent memory frequently, thus incurring non-trivial synchronization overhead. To mitigate this issue, we propose two techniques. First, we use non-volatile STT-RAM as scratchpad memory on chip to store recovery information, thereby eliminating synchronization cost in the logging phase due to the avoidance of off-chip logging operations. Second, we present an adaptive synchronization policy based on caching modes in terms of data access patterns, thereby eliminating unnecessary synchronization cost in the checkpoint phase. Evaluation results indicate that the two techniques improve the overall performance from 2.15x to 2.39x compared with conventional transactional persistent memory.

关键词： crash consistency synchronization cost persistent memory power failure mobile system

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Evaluating and Constraining Hardware Assertions with Absent Scenarios

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Journal of computer Science & Technology 2020年第5期35卷 1198-1216页

作者： Hui-Na Chao Hua-Wei Li Xiaoyu Song Tian-Cheng Wang Xiao-Wei Li State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China Peng Cheng Laboratory Shenzhen 518052China Department of Electrical and Computing Engineering Portland State UniversityPortlandOR 97207U.S.A.

Mining from simulation data of the golden model in hardware design verification is an effective solution to assertion *** the simulation data is inherently incomplete,it is necessary to evaluate the truth values of the mined *** paper presents an approach to evaluating and constraining hardware assertions with absent scenarios.A Belief-fail Rate metric is proposed to predict the truth/falseness of generated *** considering both the occurrences of free variable assignments and the conflicts of absent scenarios,we use the metric to sort true assertions in higher ranking and false assertions in lower *** Belief-failRate guided assertion constraining method leverages the quality of generated *** experimental results show that the Belief-failRate framework performs better than the existing *** addition,the assertion evaluating and constraining procedure can find more assertions that cover new design functionality in comparison with the previous methods.

关键词： hardware formal verification assertion generation data mining assertion evaluation assertion coverage

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Cs 728 nm Laser Spectroscopy and Faraday Atomic Filter

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Chinese Physics Letters 2014年第12期31卷 27-30页

作者：刘忠征陶智明蒋招杰陈景标 State Key Laboratory of Advanced Optical Communication System and Network Institute of Quantum Electronics School of Electronics Engineering ~ Computer Science Peking University Beijing 100871 College of Science Guizhou University of Engineering Science Bijie 551700

The laser spectroscopy of alkali-metal vapor is widely used in a number of applications, such as the Faraday anomalous dispersion optical fil- ter （FADOF）, the active optical clock, and wavelength ***＇ The Cs electrodeless dis- charge vapor lamp has rich spectra, including 455 nm, 459 nm, 728 nm, 852 nm, 1359 nm, and 1470 nm. The 852 nm laser pumping atoms from 6S1/2 to 6P3/2 have been used in *** 1359nm wave- length transited from 7S1/2 to 6P1/2 of Cs atoms can be used in the field of active optical clocks. The concept of active optical clocks has been proposed since 2005. Due to its good performance in sta- bility, the active optical clock has been extensively in- vestigated theoretically and experimentally in recent years, such as the two-level active optical clock, and three-level active optical clock. When considering the performance of the active optical clock, we hope to reduce the second-order Doppler shift in thermal atomic beam and the light shift induced by the pump- ing laser. To solve this issue, our group has recently proposed a four-level active optical clock, such as K 1252.2nm, Cs 1469nm, Rb 1366.9nm and Rb 728 nm. Moreover, the Rb 728 nm four-level quantum system has potentially a better performance than three long wavelength ones of Rb.

关键词： LASER spectroscopy CESIUM FARADAY effect INDUCTION lamps PHASE transformations (Physics) LIGHT filters

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BTMD: A framework of binary translation based malcode detector

BTMD: A framework of binary translation based malcode detect...

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4th International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, CyberC 2012

作者： Shan, Zheng Guo, Haoran Pang, Jianmin Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China National Digital Switching System Engineering and Technology Research Center Zhengzhou China

ISBN: (纸本)9780769548104

Binary Translation technology is used to convert binary code of one Instruction Set architecture (ISA) into another. This technology can solve the software-inheritance problem and ISA-compatibility between different computers architecture. In this paper, we describe BTMD (Binary Translation based Malcode Detector), a novel framework that exploits static and dynamic binary translation features to detect broad spectrum malware and prevent its execution. By operating directly on binary code with MD Rules on the availability of source code, BTMD is appropriate for translating low-level binary code to high-level proper representation, obtaining CFG (Control Flow Graph) and other high-level Control Structure by MD Parser. Then Critical API Graph based on CFG is generated to do sub graph matching with the defined Malware Behavior Template. MD Engine in BTMD is called to undertake the process to take on the remaining code analysis. Compared with other detection approaches, BTMD is found to be very efficient in terms of detection capability and false alarm rate. © 2012 IEEE.

关键词： Binary codes

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From laboratory to on-site operation:Reevaluation of empirically based electric water chiller models

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Building Simulation 2022年第2期15卷 213-232页

作者： Bin Zhang Shijun You Sheng Wang Xiaoxiao Ding Chuang Wang Yan Gao School of Environmental Science and Engineering Tianjin UniversityTianjin 300072China State Key Laboratory of Air-Conditioning Equipment and System Energy Conservation Zhuhai 519070China Guangdong Key Laboratory of Refrigeration Equipment and Energy Conservation Technology Zhuhai 519070China Beijing Key Laboratory of Heating Gas SupplyVentilating and Air Conditioning EngineeringBeijing University of Civil Engineering and ArchitectureBeijing 100044China Beijing Advanced Innovation Center for Future Urban Design Beijing University of Civil Engineering and ArchitectureBeijing 100044China

Chiller model is a key factor to building energy simulation and chiller performance *** spread of new types of electric water chillers that have higher performance and wider operating range,new challenges have been faced by building energy simulation tools and their chiller *** work takes a new type of electric water chiller as a case study and reevaluates eight typical empirically based models for predicting the energy performance of electric water chiller to verify whether they are suitable for the new type of chiller,using both laboratory test data from chiller manufacturer and online monitoring data from on-site operation of a central cooling plant with chillers of the same *** prediction ability of the chiller models(including model prediction accuracy and generation ability)in laboratory test and on-site operation situations are *** results show that the existing models can well describe the chiller performance in the laboratory test situation but perform poorly in the on-site operation *** the best two models in the laboratory dataset,the overall prediction errors of DOE-2 and GN model increase more than 250%and 75%respectively in the field *** big discrepancy of model prediction accuracy in the two situations is mainly due to the differences of evaporator and condenser water flow rates between the laboratory and on-site operation datasets,which indicates the limitations of the empirical chiller models and implies further research in future in order to improve the suitability and reliability of chiller model.

关键词： electric water chiller performance model model validation model prediction ability variable water flow rates

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A Parameter-Centric Approach for Enhancing Misalignment Tolerance in Wireless Power Transfer systems

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IEEE Transactions on Power Electronics 2025年

作者： Yuan, Zhaoyang Yang, Qingxin Cai, Changsong Zhang, Pengcheng Wang, Ran Ma, Xianjie Lin, Hongjian Saeedifard, Maryam Wuhan University Hubei Key Laboratory of Power Equipment & System Security for Integrated Energy School of Electrical Engineering and Automation Wuhan 430072 China Tianjin University of Technology Tianjin 300384 China Tsinghua University Department of Electrical Engineering Beijing 100084 China Heze Power Supply Company State Grid Shandong Electric Power Company Heze 274000 China Laixi Power Supply Company State Grid Shandong Electric Power Company Qingdao 266600 China University of Alberta Department of Electrical and Computer Engineering T6G 2R3 AB Canada Georgia Institute of Technology School of Electrical and Computer Engineering Atlanta 30332 GA United States

This paper introduces a misalignment-tolerant design method for wireless power transfer (WPT) systems by optimization of compensation network parameters. Leveraging the derivation of two-port impedance parameters and adjoint sensitivity analysis, the coupling misalignment characteristics of the system are assessed. Subsequently, a parameter-centric misalignment tolerant approach, independent of the coil structure, is established through a linear fitting method. The proposed approach ensures zero-voltage switching (ZVS) and facilitates efficient stable constant current (CC) output. Experimental validation is performed on a scaled-down 500-W rated SS-compensated WPT prototype equipped with non-specialized square-shaped coils, demonstrating the effectiveness of the proposed approach. The proposed method enhances the SS-compensated system's ability to tolerate both horizontal and vertical misalignments, surpassing the performance of conventional SS topologies. Specifically, the system achieves over 85% efficiency within the misalignment tolerance range, with a peak efficiency of 93.2%. Additionally, the load current variation remains within 5.8% for 100 mm x-misalignment and -15 to +50 mm z-misalignment. © 1986-2012 IEEE.

关键词： constant current (CC) output misalignment tolerance parameter-centric optimization Wireless power transfer (WPT) zero-voltage switching (ZVS)

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