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2011 6th IEEE Joint International Information Technology and Artificial Intelligence Conference, ITAIC 2011

作者： Zhang, Songmei Yao, Shan Ye, Xin'En Xia, Chunhe State Key Laboratory of Virtual Reality Technology and System School of Computer Science and Engineering Beihang University Beijing 100191 China

ISBN: (纸本)9781424486236

With the rapid development of the Internet, the network structure becomes larger and more complicated and attacking methods are more sophisticated, too. To enhance network security, Network Security Situation Analysis (NSSA) technology is a research hot spot in the network security domain. But at present, the NSSA framework and model which not only analyze the affected results of the network security but also the process how the network security is affected are less. In this paper, a novel NSSA framework is presented. The framework includes two parts: calculate the Network Security Situation Value (NSSV) and discover intrusion processes. NSSA quantitative assesses the impact on network security caused by attacks upon Analytical Hierarchy Process (AHP) and hierarchical network structure. Based on attack classification, intrusion processes discover the process how network security is affected. At last from the experiments results, NSSV exactly changes as attacks take place and the accurate intrusion processes are discovered. The applicability of the framework and algorithms are verified. © 2011 IEEE.

关键词： Network security

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SimRC: An architecture modeling and simulator generation tool for reconfigurable computing development

SimRC: An architecture modeling and simulator generation too...

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IASTED International Conference on Modelling, Simulation, and Identification, MSI 2009

作者： Liu, Yuexiao Gao, Xiaopeng Wu, Xingbo Lv, Liangshuang State Key Laboratory of Virtual Reality Technology and System School of Computer Science and Engineering Beihang University Beijing 100191 China

ISBN: (纸本)9780889868106

A modeling and simulation tool called SimRC is described in this paper. It is dedicated to improve the efficiency of reconfigurable computing development. In SimRC, a new architecture description language is designed for architecture modeling, and the target architecture simulator is generated according to that model with our code generation approach. In this way, SimRC achieves the general purpose in a certain scope. The results of the preliminary experiments show that not only SimRC is able to model various architectures, but also it achieves the high simulation efficiency.

关键词： Simulators

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Diva: A dataflow programming model and its runtime support in java virtual machine

Diva: A dataflow programming model and its runtime support i...

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13th IEEE Asia-Pacific computer systems architecture Conference, ACSAC 2008

作者： Yang, Chen Bin, Fan Lujie, Zhong Chengyong, Wu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China Graduate School of the Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424426836

Microprocessors have turned to multicore, i.e. multiple processor cores, along with some levels of on-chip caches and interconnection networks, integrated on a singe chip. However, it brings challenges on how to program these processors effectively and efficiently, which is known as the "Programming Wall". This paper proposes a systematic approach to attack the problem. We describe an extension of Java programming language with dataflow paradigm and transactional memory. Our approach alleviates the difficulties of parallel programming by providing a higher level of abstraction and relieving programmers of low-level threading and locking details. We also describe the design of a runtime system to support and optimize for the extension. We have implemented a prototype based on Apache Harmony DRL Virtual Machine. Preliminary experimental results on a 16-core SMP machine show that our approach achieves reasonable scalability and can adapt to the variance of available hardware resources. © 2008 IEEE.

关键词： Parallel programming

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Localized random access scan: Towards low area and routing overhead

Localized random access scan: Towards low area and routing o...

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2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Hu, Yu Fu, Xiang Fan, Xiaoxin Fujiwara, Hideo Key Laboratory of Computer System and Architecture Institute of Computing Technology CAS Beijing 100080 China 8916-5 Takayama Ikoma Nara 630-0192 Japan

ISBN: (纸本)9781424419227

Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead. ©2008 IEEE.

关键词： Multiplexing equipment

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Design of new hash mapping functions

Design of new hash mapping functions

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IEEE 9th International Conference on computer and Information Technology, CIT 2009

作者： Song, Fenglong Liu, Zhiyong Fan, Dongrui Zhang, Junchao Yu, Lei Yuan, Nan Lin, Wei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

Conflict can decrease performance of computer severely, such as bank conflicts reduce bandwidth of interleave multibank memory systems and conflict misses reduce effective on-chip capacity, and this incurs much conflict miss further. Conflicts can be avoided by a suitable address mapping scheme which maps the most frequently occurring patterns conflictfree. In this paper, we present a new XOR-based mapping scheme, called XORM, which focuses on multi-bank shared cache of on-chip many-core architecture. The XORM mapping scheme can map arbitrary bits of address to set indices and compute each set index bit as XOR of a transpositional subset of the bits in the address. Then, we analyze necessary characteristics of an address mapping scheme to avoid conflict in many-core architecture. Next, we give a case study to design optimal hash functions based on XORM scheme for skewedassociative cache. Finally, we introduce another case study, in which we illustrate how to design an XORM mapping scheme with lower implementation cost, complexity and computing latency in shared cache of chipped many-core architecture. The evaluated results show the effectiveness of XORM mapping scheme. © 2009 IEEE.

关键词： Hash functions

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A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults

A design- for-diagnosis technique for diagnosing both scan c...

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2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Wang, Fei Hu, Yu Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China Graduate University Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424419227

The amount of die area consumed by scan chains and scan control circuit can range from 15%∼30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a design-for-diagnosis (DFD) technique is proposed to diagnose faulty scan chains precisely and efficiently, moreover, with the assistant of the proposed technique, the conventional logic diagnostic process can be carried on with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can still be applied to our design. Experiments on ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique. ©2008 IEEE.

关键词： Chains

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Dynamic Modeling for SCR system of Coal Fired Power Plant 35

Dynamic Modeling for SCR System of Coal Fired Power Plant

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第35届中国控制会议

作者： QIN Tianmu YANG Tingting LV You HONG Feng YAO Qi State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources School of Control and Computer EngineeringNorth China Electric Power University

ISBN: (纸本)9781509009107

The dynamic model of the selective catalyst reduction（SCR） system is constructed based on the mechanism of denitration reactions. The adsorption-desorption of the reactants NH and NOx and the reactions between them are addressed independently. The model is verified by the actual operation data and the results show that the model reflects the dynamic characteristics of SCR system accurately. Furthermore, the effects of temperature and molar ratio of NH/NOx on the SCR reactions are analyzed. The simulation results show that the surface coverage and the denitration efficiency increase with temperature when the concentration of NOx and NH are constant. Similarity, both of the two indexes increase with molar ratio and there is no change in ammonia escape.

关键词： selective catalyst reduction(SCR) denitration dynamic model mechanism model

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BTBench: A Benchmark for Comprehensive Binary Translation Performance Evaluation

BTBench: A Benchmark for Comprehensive Binary Translation Pe...

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2024 IEEE International Symposium on Performance Analysis of systems and Software, ISPASS 2024

作者： Li, Xinyu Lan, Yanzhi Niu, Gen Xue, Feng Zhang, Fuxin Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences State Key Laboratory of Computer Architecture China

ISBN: (纸本)9798350376388

Binary translation serves as a fundamental technol-ogy for instruction set emulation, system virtualization, runtime instrumentation, and numerous other applications. Many techniques have been proposed to enhance the efficiency of binary translation systems. However, imprecise performance evaluation leads to potential performance shortcomings of binary translators in real-world applications. Previous studies primarily employ CPU benchmarks, which may overlook performance issues spe-cific to binary translators and fail to guide for optimizing binary translation. To address this issue, we propose a new benchmark suite named BTBench(Binary Translation Benchmark), which provides a convenient, portable, and comprehensive solution. BT-Bench takes into account the inherent attributes of binary trans-lators, such as translation and code-cache lookup overhead. We carefully select benchmarks that offer comprehensive coverage and align with real-world application scenarios. To validate the effectiveness of BTBench, we conducted rigorous experimentation on four widely-used binary translators. The analysis of the results reveals that, compared to existing CPU benchmarks, BTBench is better suited for identifying potential performance shortcomings, providing invaluable insights for future optimization efforts. The BTBench benchmark suite is publicly available 1 • © 2024 IEEE.

关键词： Benchmarking

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NfvInsight:A Framework for Automatically Deploying and Benchmarking VNF Chains

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Journal of computer Science & Technology 2022年第3期37卷 680-698页

作者： Tian-Ni Xu Hai-Feng Sun Di Zhang Xiao-Ming Zhou Xiu-Feng Sui Sa Wang Qun Huang Yun-Gang Bao State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China University of Chinese Academy of Sciences Beijing 100049China School of Information and Electronics Beijing Institute of TechnologyBeijing 100081China Peng Cheng Laboratory Shenzhen 518055China Department of Computer Science and Technology Peking UniversityBeijing 100871China

With the advent of virtualization techniques and software-defined networking(SDN),network function virtualization(NFV)shifts network functions(NFs)from hardware implementations to software appliances,between which exists a performance *** to narrow the gap is an essential issue of current NFV ***,the cumbersomeness of deployment,the water pipe effect of virtual network function(VNF)chains,and the complexity of the system software stack together make it tough to figure out the cause of low performance in the NFV *** pinpoint the NFV system performance,we propose NfvInsight,a framework for automatic deployment and benchmarking VNF *** framework tackles the challenges in NFV performance *** framework components include chain graph generation,automatic deployment,and fine granularity *** design and implementation of each component have their *** the best of our knowledge,we make the first attempt to collect rules forming a knowledge base for generating reasonable chain *** deploys the generated chain graphs automatically,which frees the network operators from executing at least 391 lines of bash commands for a single *** diagnose the performance bottleneck,NfvInsight collects metrics from multiple layers of the software ***,we collect the network stack latency distribution ingeniously,introducing only less than 2.2%*** showcase the convenience and usability of NfvInsight in finding bottlenecks for both VNF chains and the underlying *** our framework,we find several design flaws of the network stack,which are unsuitable for packet forwarding inside one single server under the NFV *** optimization for these flaws gains at most 3x performance improvement.

关键词： network function virtualization(NFV) service chain performance bottleneck network stack latency

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A microscopic view on community detection in complex networks

A microscopic view on community detection in complex network...

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2nd PhD Workshop on Information and Knowledge Management, PIKM'08, Co-located with the 17th ACM Conference on Information and Knowledge Management, CIKM'08

作者： Wang, Yang Song, Huaiming Wang, Weiping An, Mingyuan Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781605583877

The community structure is a basic characteristic of complex networks. A strong community structure has high modularity. It has been proven an NP-Complete problem to identify the community structure with the highest modularity. Many approximate algorithms have been proposed to alleviate the problem. However, they suffer from inefficiency or low quality. In this paper, we propose a two-step method. The first step of our method analyze the vertex similarity of the network, which is a microscopic view. If a pair of vertices are similar enough, they will be put into the same community. The second step of our method focuses on the increment of modularity of the similarity-based communities generated by the first step. If the number of edges between two communities is greater than the expected number based on random choice, the two communities will be merged. The second step is implemented by the CNM algorithm or its improvement CNM+HE'. The similarity-based community remedies the defect on microscope introduced by CNM or CNM+HE'. Our method runs efficiently and finds meaningful communities effectively. We tested the method on more than twenty datasets. The modularity of community structure found by the method is higher than the state-of-the-art algorithm. Copyright 2008 ACM.

关键词： Complex networks

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