Homology modeling, as a successful protein structure prediction method, has two major deficiencies, I.e., the lack of the templates (known structures), and the accuracy of alignment between the query (unknown structur...
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Homology modeling, as a successful protein structure prediction method, has two major deficiencies, I.e., the lack of the templates (known structures), and the accuracy of alignment between the query (unknown structure) and its templates. To solve these problems, we have constructed a conservative domain clustering template database, and proposed a profile-based alignment algorithm based on the profile extracted from each domain clustering in the database. The extracted profile can well represent the information of the sequence and structure as well Compared with other alignment methods, such as T-coffee and Smith-Waterman, our results show that with this method it's possible to obtain a higher hit rate for template searching and a more accurate and reliable query-template alignment. Therefore,the quality of protein structure prediction can be improved.
As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performan...
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As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N+M is proposed to improve N-core processors'yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors'performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8% degradation with negligible computing time.
The advances of containers have significantly promoted the development of microservice architecture. This architecture splits a monolithic application into multiple independent components and the container orchestrato...
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Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of ...
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Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing using path delay fault (PDF) model and single path sensitization criterion. An effective path selection and grouping method is introduced, which could quickly and accurately identify paths whose delay falls into a given delay span. Several techniques are used to improve the efficiency of the testable path selection procedure. Experimental results on ISCAS'89 benchmark circuits show that the proposed method could achieve high transition fault coverage and high test quality of SDDs with low CPU time.
This paper presents a new approach to reduce finite state machines with respect to a CTL formula to alleviate state explosion problem. Reduction is achieved by removing parts useless to the formula of original machine...
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This paper presents a new approach to reduce finite state machines with respect to a CTL formula to alleviate state explosion problem. Reduction is achieved by removing parts useless to the formula of original machines. The main contribution of this paper is to exploit relations among subformulas of the CTL formula so as to gain more reduction, as well as to extend traditional pruning method, which handles only existential formulas, to handle universal formulas. Based on this kind of reduction, verification of a large system, which usually consists of several components, can be done by evaluating properties on a reduced version of the system, which is built by composing components of the system one by one while doing reduction after each composition. Experimental results show the effectiveness of the approach. Especially when a property is written in a more detailed way, that is to describe the system part by part, the approach has a great potential.
In wireless sensor networks (WSNs), a faulty sensor may produce incorrect data and transmit them to the other sensors. This would consume the limited energy and bandwidth of WSNs. Furthermore, the base station may mak...
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In wireless sensor networks (WSNs), a faulty sensor may produce incorrect data and transmit them to the other sensors. This would consume the limited energy and bandwidth of WSNs. Furthermore, the base station may make inappropriate decisions when it receives the incorrect data sent by the faulty sensors. To solve these problems, this paper develops an online distributed algorithm to detect such faults by exploring the weighted majority vote scheme. Considering the spatial correlations in WSNs, a faulty sensor can diagnose itself through utilizing the spatial and time information provided by its neighbor sensors. Simulation results show that even when as many as 30% of the sensors are faulty, over 95% of faults can be correctly detected with our algorithm. These results indicate that the proposed algorithm has excellent performance in detecting fault of sensor measurements in WSNs.
Despite a number of innovative computersystems with high capacity memory have been built, the design principles behind an operating system kernel have remained unchanged for decades. We argue that kernel parameters i...
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DRAM access traces (i.e., off-chip memory references) can be extremely valuable for the design of memory subsystems and performance tuning of software. Hardware snooping on the off-chip memory interface is an effectiv...
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In this paper, we focus on generation of a universal path candidate set V that contains testable long paths for delay testing. Some strategies are presented to speed up the depth first search procedure of U generation...
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In this paper, we focus on generation of a universal path candidate set V that contains testable long paths for delay testing. Some strategies are presented to speed up the depth first search procedure of U generation, targeting the reduction of sensitization criteria checking times. Experimental results illustrate that our approach achieves an 8X speedup on average in comparison with the traditional depth first search approach.
As a primary method for functional verification of microprocessors, simulation-based verification has received extensive studies over the last decade. Most investigations have been dedicated to the generation of stimu...
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As a primary method for functional verification of microprocessors, simulation-based verification has received extensive studies over the last decade. Most investigations have been dedicated to the generation of stimuli (test cases), while relatively few has focused on explicitly reducing the redundant stimuli among the generated ones. In this paper, we propose an on-the-fly approach for reducing the stimuli redundancy based on machine learning techniques, which can learn from new knowledge in every cycle of simulation-based verification. Our approach can be easily embedded in traditional framework of simulation-based functional verification, and the experiments on an industrial microprocessor have validated that the approach is effective and efficient.
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