检索结果-内蒙古大学图书馆

NfvInsight:A Framework for Automatically Deploying and Benchmarking VNF Chains

Journal of computer Science & Technology 2022年第3期37卷 680-698页

作者： Tian-Ni Xu Hai-Feng Sun Di Zhang Xiao-Ming Zhou Xiu-Feng Sui Sa Wang Qun Huang Yun-Gang Bao State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China University of Chinese Academy of Sciences Beijing 100049China School of Information and Electronics Beijing Institute of TechnologyBeijing 100081China Peng Cheng Laboratory Shenzhen 518055China Department of Computer Science and Technology Peking UniversityBeijing 100871China

With the advent of virtualization techniques and software-defined networking(SDN),network function virtualization(NFV)shifts network functions(NFs)from hardware implementations to software appliances,between which exists a performance *** to narrow the gap is an essential issue of current NFV ***,the cumbersomeness of deployment,the water pipe effect of virtual network function(VNF)chains,and the complexity of the system software stack together make it tough to figure out the cause of low performance in the NFV *** pinpoint the NFV system performance,we propose NfvInsight,a framework for automatic deployment and benchmarking VNF *** framework tackles the challenges in NFV performance *** framework components include chain graph generation,automatic deployment,and fine granularity *** design and implementation of each component have their *** the best of our knowledge,we make the first attempt to collect rules forming a knowledge base for generating reasonable chain *** deploys the generated chain graphs automatically,which frees the network operators from executing at least 391 lines of bash commands for a single *** diagnose the performance bottleneck,NfvInsight collects metrics from multiple layers of the software ***,we collect the network stack latency distribution ingeniously,introducing only less than 2.2%*** showcase the convenience and usability of NfvInsight in finding bottlenecks for both VNF chains and the underlying *** our framework,we find several design flaws of the network stack,which are unsuitable for packet forwarding inside one single server under the NFV *** optimization for these flaws gains at most 3x performance improvement.

关键词： network function virtualization(NFV) service chain performance bottleneck network stack latency

来源：评论

学校读者我要写书评

暂无评论

Accelerate Smoothed Particle Hydrodynamics using GPU

Accelerate Smoothed Particle Hydrodynamics using GPU

引用

2010 IEEE Youth Conference on Information, Computing and Telecommunications, YC-ICT 2010

作者： Gao, Xiaopeng Wang, Zhiqiang Wan, Han Long, Xiang State Key Laboratory of Virtual Reality Technology and System School of Computer Science and Engineering Beihang University 100191 Beijing China

ISBN: (纸本)9781424488841

Physic-based fluid simulation is used extensively nowadays;however the traditional serial algorithm can't satisfy the realtime requirement due to its complexity and compute-intensive. The development of modern GPU makes this possible. In this paper, a Smoothed Particle Hydrodynamics (SPH) method for incompressible fluid was implemented using CUDA on GPU. Since the algorithm was executed on the GPU entirely, the method can take full advantage of massive computational power of modern graphics hardware. The experiment results show that our GPU based SPH implementation can achieve the rate of 89 frames per second in the simulation of 102K particles and gain nearly 140x speedups compared with the serial algorithm. © 2010 IEEE.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Simplification for texture mapping models with mesh segmentation

Simplification for texture mapping models with mesh segmenta...

引用

2010 16th International Conference on Virtual systems and Multimedia, VSMM 2010

作者： Wang, Lili Ma, Zhiqiang Xue, Bing Shen, Zhe State Key Laboratory of Virtual Reality Technology and System School of Computer Science and Engineering Beihang University Beijing 100191 China

ISBN: (纸本)9781424490264

To reduce the loss of visual details in simplification for textured meshes, this paper presents a simplification method based on mesh segmentation. Firstly, the model is partitioned into some sub-meshes according to their properties of appearance, such as texture, normal, etc. Thus, the correlation between sub-meshes can be decreased. Then, we calculate the error metric for the edge collapse in each sub-mesh. Lastly, we merge the simplified sub-meshes and fix the gap among them to regain an integrated mesh. Because the properties of appearance are used to separate the high-frequency details from low-frequency ones, our approach decreases the loss of the detailed. Therefore, we can not only keep the over whole contours of the model, but also maintain better geometric and appearance details. The results of experiments demonstrate our mesh segmentation based method is effective. ©2010 IEEE.

关键词： Mesh generation

来源：评论

学校读者我要写书评

暂无评论

Chameleon: A data organization transformation scheme for big data systems 14

Chameleon: A data organization transformation scheme for big...

引用

11th ACM International Conference on Computing Frontiers, CF 2014

作者： Pan, Fengfeng Yue, Yinliang Xiong, Jin State Key Laboratory of Computer Architecture Institute of Computing Technology CAS China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450328708

Big data system requires multiple types of data organi-zations to effciently support various operations. It is well known that in-place update index, unordered log structured index and ordered log structured index are three typical data organizations which are designed to meet different workload requirements respectively. Differentiated workload requirements in different phase of the data life-cycle lead to data organization transformation. However, typical sequential data organization transformation not only incurs extremely long time, but also signicant energy consumption. In this paper, we propose Chameleon, a novel data organization transformation scheme for replication based big data system. The goal of Chameleon is to signi-cantly shorten the data organization transformation process and improve the write performance and the subsequent read performance through data organization transformation, meanwhile eliminate the additional hardware and energy costs by reusing the mirrored disks. For each put request, Chameleon keeps two copies of the key-value pair. One in its normal place and organized in ordered log structured index, and the other in relatively high performance log disk and organized in unordered log structured index. By spreading destaging I/O activities among short idle time slots, key-value pairs are transformed from write-optimized index to read-optimized index. Extensive experimental evaluation based on our prototype shows that Chameleon can shorten the time of data organization transformation and enhance energy effciency and performance. © is held by the owner/authors.

关键词： Big data

来源：评论

学校读者我要写书评

暂无评论

Determination of the principal components for the optimal detection performance of a combined index

Determination of the principal components for the optimal de...

引用

第25届中国控制与决策会议

作者： Tian Qiu Xiaojing Bai Xiyu Zheng Xiang Zhu State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources School of Control and Computer Engineering North China Electric Power University

ISBN: (纸本)9781467355339

In process monitoring, faults might be completely detected by or or both of them. However, one index rather than two indices is preferred to monitor a process in practice. The number of principal components (PCs) in principal component analysis (PCA) impacts the fault detection performance obviously. In this paper, we focus on developing a selection criterion for the number of the PCs based on the best detection performance of the combined index and discussing the uncertainty of PCA model through cross validation. The simulation demonstrates that one index has a good detection performance and simplifies the detection system.

关键词： principal component analysis (PCA), fault detection, detection performance, fault amplitude

来源：评论

学校读者我要写书评

暂无评论

A Hybrid Circular Queue Method for Iterative Stencil Computations on GPUs

引用

Journal of computer Science & Technology 2012年第1期27卷 57-74页

作者： Yang Yang Hui-Min Cui Xiao-Bing Feng Jing-Ling Xue State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China Programming Languages and Compilers Group School of Computer Science and Engineering University of New South WalesSydneyNSW 2052Australia

In this paper, we present a hybrid circular queue method that can significantly boost the performance of stencil computations on GPU by carefully balancing usage of registers and shared-memory. Unlike earlier methods that rely on circular queues predominantly implemented using indirectly addressable shared memory, our hybrid method exploits a new reuse pattern spanning across the multiple time steps in stencil computations so that circular queues can be implemented by both shared memory and registers effectively in a balanced manner. We describe a framework that automatically finds the best placement of data in registers and shared memory in order to maximize the performance of stencil computations. Validation using four different types of stencils on three different GPU platforms shows that our hybrid method achieves speedups up to 2.93X over methods that use circular queues implemented with shared-memory only.

关键词： stencil computation circular queue GPU occupancy register

来源：评论

学校读者我要写书评

暂无评论

The rise of high-throughput computing

引用

Frontiers of Information Technology & Electronic Engineering 2018年第10期19卷 1245-1250页

作者： Ning-hui SUN Yun-gang BAO Dong-rui FAN State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesUniversity of Chinese Academy of Sciences

In recent years, the advent of emerging computing applications, such as cloud computing, artificial intelligence, and the Internet of Things, has led to three common requirements in computer system design： high utilization, high throughput, and low latency. Herein, these are referred to as the requirements of ＇high-throughput computing （HTC）＇. We further propose a new indicator called ＇sysentropy＇ for measuring the degree of chaos and uncertainty within a computer system. We argue that unlike the designs of traditional computing systems that pursue high performance and low power consumption, HTC should aim at achieving low sysentropy. However, from the perspective of computer architecture, HTC faces two major challenges that relate to （1） the full exploitation of the application＇s data parallelism and execution concurrency to achieve high throughput, and （2） the achievement of low latency, even in the cases at which severe contention occurs in data paths with high utilization. To overcome these two challenges, we introduce two techniques： on-chip data flow architecture and labeled von Neumann architecture. We build two prototypes that can achieve high throughput and low latency, thereby significantly reducing sysentropy.

关键词： High-throughput computing Sysentropy Information superbahn

来源：评论

学校读者我要写书评

暂无评论

Exploiting idle register classes for fast spill destination

Exploiting idle register classes for fast spill destination

引用

22nd ACM International Conference on Supercomputing, ICS'08

作者： Lu, Fang Wang, Lei Feng, Xiaobing Li, Zhiyuan Zhang, Zhaoqing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100191 China Department of Computer Sciences Purdue University West Lafayette IN 47906 United States

ISBN: (纸本)9781605581583

On today's microprocessors, there often exist several different types of registers, e.g. general purpose registers and floating point registers. A given program may use one type of registers much more frequently than other types. This creates an opportunity to employ the infrequently used registers as spill destinations for the more frequently used register types. In this paper, we present a code optimization method named idle register exploitation (IRE) to exploit such opportunities. We developed a model, called the IRE model, or IREM, to determine the static performance gains of IRE versus spilling to the stack. On a microprocessor with fast data paths between different types of registers, we find that IRE method speeds up the execution of the SPECint benchmark suite from 1.7% to 10%. In contrast, on microprocessors with less efficient data transfer paths, the performance gain is limited. In some cases, performance may even suffer degradation. This result argues strongly for the adoption of fast data paths between different types of registers for the purpose of reducing register spills, which is important in view of the increased significance of memory bottlenecks on future microprocessors. Copyright 2008 ACM.

关键词： Data transfer

来源：评论

学校读者我要写书评

暂无评论

Extendable pattern-oriented optimization directives

Extendable pattern-oriented optimization directives

引用

作者： Cui, Huimin Xue, Jingling Wang, Lei Yang, Yang Feng, Xiaobing Fan, Dongrui Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Beijing China School of Computer Science and Engineering University of New South Wales Sydney NSW Australia

Algorithm-specific, that is, semantic-specific optimizations have been observed to bring significant performance gains, especially for a diverse set of multi/many-core architectures. However, current programming models and compiler technologies for the state-of-the-art architectures do not exploit well these performance opportunities. In this article, we propose a pattern-making methodology that enables algorithm-specific optimizations to be encapsulated into "optimization patterns". Such optimization patterns are expressed in terms of preprocessor directives so that simple annotations can result in significant performance improvements. To validate this new methodology, a framework, named EPOD, is developed to map these directives into the underlying optimization schemes for a particular architecture. It is difficult to create an exact performance model to determine an optimal or near-optimal optimization scheme (including which optimizations to apply and in which order) for a specific application, due to the complexity of applications and architectures. However, it is trackable to build individual optimization components and let compiler developers synthesize an optimization scheme from these components. Therefore, our EPOD framework provides an Optimization Programming Interface (OPI) for compiler developers to define new optimization schemes. Thus, new patterns can be integrated into EPOD in a flexible manner. We have identified and implemented a number of optimization patterns for three representative computer platforms. Our experimental results show that a pattern-guided compiler can outperform the state-of-theart compilers and even achieve performance as competitive as hand-tuned code. Therefore, such a patternmaking methodology represents an encouraging direction for domain experts' experience and knowledge to be integrated into general-purpose compilers. © 2012 ACM.

关键词： Semantics

来源：评论

学校读者我要写书评

暂无评论

The Sunway Taihu Light supercomputer:system and applications

引用

Science China(Information Sciences) 2016年第7期59卷 113-128页

作者： Haohuan FU Junfeng LIAO Jinzhe YANG Lanning WANG Zhenya SONG Xiaomeng HUANG Chao YANG Wei XUE Fangfang LIU Fangli QIAO Wei ZHAO Xunqiang YIN Chaofeng HOU Chenglong ZHANG Wei GE Jian ZHANG Yangang WANG Chunbo ZHOU Guangwen YANG Ministry of Education Key Laboratory for Earth System Modeling and Center for Earth System ScienceTsinghua University National Supercomputing Center in Wuxi Department of Computer Science and Technology Tsinghua University College of Global Change and Earth System Science Beijing Normal University First Institute of Oceanography State Oceanic Administration Institute of Software Chinese Academy of Sciences Institute of Process Engineering Chinese Academy of Sciences Computer Network Information Center Chinese Academy of Sciences

The Sunway Taihu Light supercomputer is the world’s first system with a peak performance greater than 100 PFlops. In this paper, we provide a detailed introduction to the Taihu Light system. In contrast with other existing heterogeneous supercomputers, which include both CPU processors and PCIe-connected many-core accelerators(NVIDIA GPU or Intel Xeon Phi), the computing power of Taihu Light is provided by a homegrown many-core SW26010 CPU that includes both the management processing elements(MPEs)and computing processing elements(CPEs) in one chip. With 260 processing elements in one CPU, a single SW26010 provides a peak performance of over three TFlops. To alleviate the memory bandwidth bottleneck in most applications, each CPE comes with a scratch pad memory, which serves as a user-controlled cache. To support the parallelization of programs on the new many-core architecture, in addition to the basic C/C++and Fortran compilers, the system provides a customized Sunway Open ACC tool that supports the Open ACC2.0 syntax. This paper also reports our preliminary efforts on developing and optimizing applications on the Taihu Light system, focusing on key application domains, such as earth system modeling, ocean surface wave modeling, atomistic simulation, and phase-field simulation.

关键词： supercomputer many-core high performance computing scientific computing computer architecture

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：