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Register-based implementation of the sparse general matrix-matrix multiplication on GPUs

ACM SIGPLAN Notices 2018年第1期53卷 407-408页

作者： Liu, Junhong He, Xin Liu, Weifeng Tan, Guangming State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China Department of Computer Science Norwegian University of Science and Technology Norway

General sparse matrix-matrix multiplication (SpGEMM) is an essential building block in a number of applications. In our work, we fully utilize GPU registers and shared memory to implement an efficient and load balance... 详细信息

ISBN: (纸本)9781450349116

关键词： Matrix algebra

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Fast and efficient parallel breadth-first search with power-law graph transformation

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Frontiers of computer Science 2022年第5期16卷 225-227页

作者： Zite JIANG Tao LIU Shuai ZHANG Mengting YUAN Haihang YOU School of Computer Science and Technology University of Chinese Academy of SciencesBeijing 100049China State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China School of Comptuer Science Wuhan UniversityWuhan 430072China

1 Introduction Most real-world graphs are large-scale but unstructured and *** of the most notable characteristics of real-world graphs is the skewed power law degree distribution[1]:most vertices have a few neighbors while a few own a large number of *** characteristics present challenges for efficient parallel graph processing,such as load imbalance,poor locality,and redundant *** from modifying the graph programming abstraction or changing the execution models on different architectures,reducing the irregularity of graph data also improves the performance of graph processing[2].For example,it is wellknown that BFS has a bad temporal locality,but it is possible to transform irregular graphs to more regular ones to improve spatial locality and gain more performance.

关键词： neighbor programming redundant

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Fast path selection for testing of small delay defects considering path correlations

Fast path selection for testing of small delay defects consi...

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28th IEEE VLSI Test Symposium, VTS10

作者： He, Zijian Lv, Tao Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of the Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424466481

Statistical timing models have been proposed to describe delay variations in very deep sub-micro process technologies, which have increasingly significant influence on circuit performance. Under a statistical timing model, testing of a path can detect potential delay failures caused by different small delay defects. Due to path correlations, the potential delay failures captured by two different paths overlap between each other more or less. It is difficult to find a given number of paths that can capture most potential delay failures. In this paper, the path selection problem is converted to a minimal space intersection problem, and a greedy path selection heuristics is proposed, the key point of which is to calculate the probability that the paths in a specified path set all meet the delay constraint. Statistical timing analysis technologies and heuristics are used in the calculation. Experimental results show that the proposed approach is time-efficient and achieves a higher probability of capturing delay failures in comparison with conventional path selection approaches. ©2010 IEEE.

关键词： Defects

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GVE: Godson-T verification engine for many-core architecture rapid prototyping and debugging

GVE: Godson-T verification engine for many-core architecture...

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2010 International Conference on Field-Programmable Technology, FPT'10

作者： Lei, Zhengmeng Zhang, Lunkai Song, Fenglong Tang, Shibin Fan, Dongrui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424489817

In this paper, we present a Godson-T Verification Engine (GVE) to rapidly prototype and debug our Godson-T many-core processor design. GVE adopts the state-of-the-art hardware platform which contains 6 Xilinx Virtex-5 LX330 FPGAs, thus permitting us to map our many-core processor and peripheral devices into it. Besides the hardware, our toolkit Godson-T Studio provides the compiler, program loader, debugger and monitor to fulfil the purpose of developing, profiling and debugging, while the accuracy loss problem is settled by our novel techniques: Check-point and ILA-Check, presented in this paper. To our experience, GVE greatly reduces the verification cycle due to its high execution speed, for example, it finishes thousands of testcases in an hour, where the software-based approach takes few days to run. And by the help of the checkpoint framework, we can easily locate the faults. Because of these features, GVE makes a great contribution to the 16-tile Godson-T tape-out Project. © 2010 IEEE.

关键词： Verification

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The design-for-testability features of a general purpose microprocessor

The design-for-testability features of a general purpose mic...

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2007 IEEE International Test Conference, ITC

作者： Wang, Da Fan, Xiaoxin Fu, Xiang Liu, Hui Wen, Ke Li, Rui Li, Huawei Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Beijing China Co. Ltd. Shanghai China

ISBN: (纸本)1424411289

This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. Major DFT solutions are implemented which can meet high-volume manufacturing (HVM) and high quality test goals. © 2007 IEEE.

关键词： Design for testability

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Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects

Test Generation for Crosstalk Glitches Considering Multiple ...

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The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

作者： Minjin Zhang Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

As the feature size continues to scale into the nanometer era, crosstalk-induced effect begins to exert a more significant influence. In this paper, we address the condition of maximum crosstalk glitch noise considering multiple coupling effects and propose a novel test generation technique for this problem. A multiple crosstalk-induced glitch fault (MCGF) model is introduced, which gives information on one or more sub-paths to be sensitized to generate transitions coupled to a victim line. The test for an MCGF is a 2-vector pattern that sensitizes the transition signal along the sub-path to each aggressor line at the maximum aggressive time (MAT), and propagates the signal on a victim line to an output. A new structure, transition map (TM), is proposed to record all the possible arrival time of a line. The MAT of a victim line is calculated based on effective coupling capacitance (ECC). Therefore, the crosstalk-induced effects can be effectively identified, and exactly activated using the generated test patterns. Experiments on ISCAS89 benchmark circuit show that the proposed technique can be applied to circuits of reasonable sizes within acceptable time.

关键词： Crosstalk Circuit faults Timing Test pattern generators system testing Noise generators Coupling circuits Capacitance Circuit noise Automatic test pattern generation

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Atmospheric Ducting Effect in Wireless Communications:Challenges and Opportunities

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Journal of Communications and Information Networks 2021年第2期6卷 101-109页

作者： Fangfang Liu Jiaxi Pan Xiangwei Zhou Geoffrey Ye Li Beijing Laboratory of Advanced Information Networks Beijing Key Laboratory of Network System Architecture and ConvergenceBeijing University of Posts and TelecommunicationsBeijing 100876China Louisiana State University Baton Rouge LA 70803USA Imperial College London London SW72AZU.K.

Atmospheric ducting has a significant impact on electromagnetic wave *** signals that are trapped and guided by the atmospheric duct can travel a much longer distance over the horizon with lower attenuation since the signal power does not spread isotropically through the *** ducting brings both challenges and opportunities to wireless *** one hand,the signals propagating in the atmospheric duct may interfere with a receiver far away as remote co-channel *** the other hand,a point-to-point link can be established directly through the atmospheric duct to enable beyond line-of-sight *** this article,the formation of the atmospheric duct and its effects on radio wave propagation are first *** solutions and standardization activities in the 3rd Generation Partnership Project(3GPP)to mitigate atmospheric duct induced remote interference are ***,the applications and design challenges of atmospheric duct enabled beyond line-of-sight communications are reviewed and future research directions are suggested.

关键词： atmospheric duct ducting channel modeling beyond line-of-sight remote interference management

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Deterministic Circular Self Test Path

Deterministic Circular Self Test Path

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第十二届全国容错计算学术会议

作者： WEN Ke HU Yu LI Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental results on ISCAS'89 benchmarks show that 100％ fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.

关键词： very large scale integration (VLSI) test built-in-self-test (BIST) circular self test path deterministic

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Poster: Revisiting linpack algorithm on large-scale CPU-GPU heterogeneous systems 25

Poster: Revisiting linpack algorithm on large-scale CPU-GPU ...

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25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2020

作者： Shui, Chaoyang Yu, Xianzhi Yan, Yujin Wang, Yinshan Meng, Ke Tan, Guangming State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China

ISBN: (纸本)9781450368186

As the widening gap between GPU computing capability and other components (CPU, PCIe bus and communication network), it’s increasingly challenging to design high performance parallel algorithms for large CPU-GPU heterogeneous systems. There are mainly two reasons. Firstly, simply offloading the kernel library to GPU incurs large volume data transfer through low-speed PCIe bus. Secondly, communication overheads through network severely affects scalability. To solve the above issues, we advocate a paradigm shift to GPU-centric and fine-grained pipelining algorithm design. By taking Linpack benchmark as a case study, the new algorithm design paradigm shows its effectiveness. Our optimized Linpack program achieves 63.79PFlops on 16384 GPUs. Its floating-point efficiency outperforms the NVIDIA proprietary counterparts by 5% on average. © 2020 Copyright held by the owner/author(s).

关键词： Graphics processing unit

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Protein Structure Prediction Based on a Domain Clustering Database

Protein Structure Prediction Based on a Domain Clustering Da...

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The 1st International Conference on Bioinformatics and Biomedical Engineering(iCBBE 2007)(首届IEEE生物信息与生物医学工程国际会议)

作者： Zhaoyun Ma Lin Xu Zhiyong Liu Fa Zhang Shengzhong Feng Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Comput Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Comput

Homology modeling, as a successful protein structure prediction method, has two major deficiencies, I.e., the lack of the templates (known structures), and the accuracy of alignment between the query (unknown structure) and its templates. To solve these problems, we have constructed a conservative domain clustering template database, and proposed a profile-based alignment algorithm based on the profile extracted from each domain clustering in the database. The extracted profile can well represent the information of the sequence and structure as well Compared with other alignment methods, such as T-coffee and Smith-Waterman, our results show that with this method it's possible to obtain a higher hit rate for template searching and a more accurate and reliable query-template alignment. Therefore,the quality of protein structure prediction can be improved.

关键词： structure prediction profile domain

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